Supporting variable line length in digital display timing...

Details Supporting variable line length in digital display timing... Supporting variable line length in digital display timing...

2006-02-28

2006-02-28

Awad, Amr A. (Department: 2673)

Computer graphics processing and selective visual display system

Display driving control circuitry

Adjusting display pixel size or pixels per given area

C345S690000, C345S691000, C345S558000, C345S003200

Reexamination Certificate

active

07006115

ABSTRACT:
A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to generate horizontal line demarkers in the V-blank (vertical blank) region. The demarkers specify the transition from one line to the other. Such a feature is useful in spread spectrum clocking (SSC) based display signals in which HSYNC signals may also not be available to determine the transitions from one line to another in the V-blank region.

REFERENCES:
patent: 4959724 (1990-09-01), Ueda
patent: 5125028 (1992-06-01), Naito
patent: 5144418 (1992-09-01), Brown et al.
patent: 5572235 (1996-11-01), Mical et al.
patent: 5757338 (1998-05-01), Bassetti et al.
patent: 6580432 (2003-06-01), Leung et al.

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