Support structures for an intelligent low power serial bus

Details Support structures for an intelligent low power serial bus Support structures for an intelligent low power serial bus

1995-08-18

1998-09-22

Auve, Glenn A.

395733, G06F 1300

Patent

active

058127968

ABSTRACT:
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a plurality of serial bus support structures. For example, the serial bus support structures can include an interrupt generation circuit, a power-on circuit, and a wake-up interrupt generation circuit, and a wake-up interrupt propagation circuit.

REFERENCES:
patent: 5119496 (1992-06-01), Nishikawa et al.
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5475854 (1995-12-01), Thomsen et al.

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