Supply voltage tolerant phase-locked loop circuit

Details Supply voltage tolerant phase-locked loop circuit Supply voltage tolerant phase-locked loop circuit

1994-09-23

1995-10-31

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 8, 331 11, 331 16, 331 17, 331 25, H03L 100

Patent

active

054633524

ABSTRACT:
A phase-locked loop design is provided that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

REFERENCES:
patent: 5302920 (1994-04-01), Bitting
Ware et al.; A 200-Mhz CMOS Phase-Locked Loop with Dual Phase Detectors; Dec. 1989; pp. 1560-1568, IEEE Journal of Solid-State Circuits, vol. 24, No. 6.
Jeong et al.; Design of PLL-Based Clock Generation Circuits, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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