Supply voltage tolerant phase-locked loop circuit

Details Supply voltage tolerant phase-locked loop circuit Supply voltage tolerant phase-locked loop circuit

1996-10-04

2000-09-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 8, 331 11, 331 16, 331 17, 331 25, H03L 100

Patent

active

RE0368741

ABSTRACT:
A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

REFERENCES:
patent: 5061907 (1991-10-01), Rasmussen
patent: 5175512 (1992-12-01), Self
patent: 5258725 (1993-11-01), Kinoshita
patent: 5302920 (1994-04-01), Bitting
patent: 5331295 (1994-07-01), Jelinek et al.
Ware et al.; "A 200-Mhz CMOS Phase-Locked Loop With Dual Phase Detectors"; Dec. 1989; pp.1560-1568, IEEE Journal of Solid-State Circuits, vol. 24, No. 6.
Jeong et al.; "Design of PLL-Based Clock Generation Circuits"; IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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