Oscillators – Ring oscillators
Reexamination Certificate
1999-02-12
2001-06-12
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C331S025000, C331S175000
Reexamination Certificate
active
06246294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to oscillator systems, and more specifically, to voltage-controlled oscillator of phase locked loop systems.
2. Description of the Related Art
Phase-locked loop circuits are known. Phase-locked loop circuits are used to provide a clock signal in conventional integrated circuit chips. Conventional phase-locked loop circuits include a conventional phase detector, a conventional amplifier, and a conventional voltage controlled oscillator. The conventional phase detector is coupled to the conventional amplifier. The conventional amplifier is coupled to the conventional oscillator.
The conventional phase detector compares two frequency signals to determine if they are equal. If they are equal, the voltage controlled oscillator locks in to a frequency of the input signal. If the two signals are not equal, the conventional phase detector generates a phase error signal that is amplified and sent to the voltage controlled oscillator. The voltage controlled oscillator uses this signal to deviate the frequency of its signal towards the frequency of the input signal.
As the speed of integrated circuit chips increases the conventional phase-locked loop circuit becomes more and more unreliable. For example, cycle-to-cycle jitter in the signal output from the voltage controlled oscillator increases. Most of this jitter results from sources within the phase-locked loop circuit. For example, in a deep sub-micron process, digital circuitry in the ultra large scale integration system makes the supply voltage particularly noisy.
Further, a problem with conventional phase-locked loop circuits is that they are unreliable in high frequency applications. Severe jitter is unacceptable in such applications. The jitter that results in a high performance system causes errors in the generated system clock and inaccuracies in clocked data. This results in a decrease in overall system speed and efficiency.
In conventional phase-locked loop circuits, there may be numerous sources of jitter. For example, one source of jitter is supply voltage noise from sources such as the conventional voltage controlled oscillator in the phase locked-loop circuit. Another source of jitter is the intrinsic noise in field effect transistors used in the phase-locked loop circuit. Still another source of noise is the noise coupling onto the controlled voltage from a phase detector or low-pass filter. Each source of jitter increases the overall jitter in the system.
Therefore, there is a need for a phase-locked loop system and a method that (1) is suitable for deep sub-micron process, (2) generates a clock signal with reduced supply voltage noise sensitivity in high frequency applications; and (3) includes a supply voltage noise immunity low jitter voltage controlled oscillator.
SUMMARY OF THE INVENTION
A system and a method of the present invention include a phase-locked loop (PLL) system and method for generating a clock signal having a low jitter characteristic. A phase-locked loop system that generates an output signal having low jitter includes a phase frequency detector, a charge pump, a PLL low-pass filter, a low jitter voltage-controlled oscillator, and a divider.
The phase frequency detector is coupled to an input signal line. The charge pump couples to the phase frequency detector, the low jitter voltage controlled oscillator, and the PLL low pass filter. The low jitter voltage controlled oscillator couples to an output signal line and to the divider. The divider couples to the phase frequency detector through a feedback signal line.
Further, the low jitter voltage controlled oscillator includes a voltage regulator, a VCO low-pass filter, and a ring oscillator. The low jitter voltage controlled oscillator may also include a current driver. The voltage regulator couples to the low-pass filter and to the input signal line. The VCO low-pass filter couples to the optional current driver and the ring oscillator. The ring oscillator couples to the charge pump, the PLL low pass filter, the output signal line, and the divider.
The input signal includes an input frequency and an input phase. The phase frequency detector receives the input signal and compares the input phase with a feedback phase of a feedback signal from the divider. If the input phase is before the feedback phase, the phase frequency detector generates an up signal. If the input phase is after the feedback phase, the phase frequency detector generates a down signal.
The charge pump receives the up signal or the down signal. If the up signal is received, the charge pump gradually increases a controlled voltage signal that is transmitted to the low jitter voltage controlled oscillator. If the charge pump receives the down signal, the charge pump gradually decreases the controlled voltage signal transmitted to the low jitter voltage controlled oscillator.
The ring oscillator of the low jitter voltage controlled oscillator receives the increasing or decreasing controlled voltage signal from the charge pump. In the voltage controlled oscillator, the voltage regulator receives a reference voltage signal. The voltage regulator uses the reference voltage to generate a voltage regulator signal that is a regulated supply voltage. This supply voltage may have a frequency that matches the frequency of the input signal. The voltage regulator reduces the low frequency supply noise in the regulated supply voltage. The regulated supply voltage passes through the low-pass filter, which filters out the high frequency noise. The resulting signal is a clean voltage supply signal, ACVDD.
The clean voltage supply signal is a DC voltage. The clean voltage supply signal may be a drive signal that assists in driving the ring oscillator. The optional driver current course may also provide an additional current source for the drive signal. The drive signal is received by each differential delay stage of the ring oscillator. The ring oscillator also receives the increasing or decreasing controlled voltage signal. The result is that if the ring oscillator receives an increasing controlled voltage signal, it generates an output signal having an increasing frequency, f
o
. If the ring oscillator receives a decreasing controlled voltage signal, it generates an output signal having a decreasing frequency, f
o
. A use of the output signal is as a clock signal having low jitter.
The present invention is beneficially used in high performance electrical systems. For example, the present invention advantageously may be operated at a broad frequency range so that a clock signal having low jitter characteristics may be generated. The low jitter clock signal increases system performance because the system may lower the time period it must budget for signal jitter.
The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.
REFERENCES:
patent: 5180995 (1993-01-01), Hayashi et al.
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patent: 5686867 (1997-11-01), Sutardja et al.
patent: 5847616 (1998-12-01), Ng et al.
patent: 5959502 (1999-09-01), Ovens et al.
Hayes, T. C., Horowitz, P., “Student Manual for the Art of Electronics,” Cambridge University Press, Chapter 9, pp. 406-430, 1989.
Horowitz, P., Hill, W., “The Art of Electronics,” Cambridge University Press, Second Edition, Chapter 9, pp. 641-655, 1989.
Fenwick & West LLP
Fujitsu Limited
Kinkead Arnold
LandOfFree
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