Superscalar processor with forward map buffer in multiple instru

Details Superscalar processor with forward map buffer in multiple instru Superscalar processor with forward map buffer in multiple instru

1997-08-21

1999-09-28

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712 23, G06F 938

Patent

active

059580437

ABSTRACT:
A multiple instruction parallel issue/execution management system including a forward map buffer for storing forward map information indicating whether or not the result value generated by execution of a given instruction is used an input operand in other instructions. The forward map buffer previously stores the forward map information for the result value, before the result value corresponding to the given instruction is actually generated, and when the result value corresponding to the given instruction is actually generated, the operands using the result value are specified by using the previously stored forward map information corresponding to the result value, and supplied to an instruction using the result value as an input operand.

REFERENCES:
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5710902 (1998-01-01), Sheaffer et al.
patent: 5802386 (1998-09-01), Kahle et al.
"Superscalar Microprocessor Design", Prentice Hall Series in Innovative Technology, Mike Johnson, pp. 30-55.

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