Superscalar processor with a multi-port reorder buffer

Details Superscalar processor with a multi-port reorder buffer Superscalar processor with a multi-port reorder buffer

1994-11-29

1996-11-12

Donaghue, Larry D.

Boots, shoes, and leggings

395376, 364DIG1, 36423222, 3642318, 364247, 3642549, G06F 930, G06F 1200

Patent

active

055749356

ABSTRACT:
A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a predetermined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state. The write transistor stack couples the write data line to the cell such that writing a first logic state on the write data line pulls the input to the cell to a low logic state, and writing a second logic state on the write data line drives the input to the cell to a high logic state. The multi-port register has application for use in a superscalar microprocessor performing out-of-order dispatch and execution and speculative execution.

REFERENCES:
patent: 5129067 (1992-07-01), Johnson
patent: 5189640 (1997-02-01), Huard et al.
IEEE Micro, Published Jun., 1991, pp. 10-13, and 63-73, Authors: Val Popescu et al., Entitled: The Metaflow Architecture.
Superscalar Microprocessor Design; author; Mike Johnson; a publication of Prentice-Hall Series in Innovative Technology; Prentice-Hall, 1991, Chapters 6 and 7 (pp. 103-146).

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