Superscalar execution unit for sequential instruction pointer up

Details Superscalar execution unit for sequential instruction pointer up Superscalar execution unit for sequential instruction pointer up

1994-01-21

1996-12-31

Shah, Alpesh M.

Boots, shoes, and leggings

395386, 39542108, 3642318, 3642613, 3642624, 364DIG1, G06F 938

Patent

active

055903517

ABSTRACT:
An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.

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