Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-08-25
2002-10-22
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S777000, C257S723000, C257S668000, C257S700000, C257S701000, C257S774000, C257S758000, C257S692000, C257S693000, C257S737000, C257S738000, C257S778000
Reexamination Certificate
active
06469374
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-239033, filed Aug. 26, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a superposed type package and a manufacturing method of the same.
Recently, the semiconductor device is often used in a condition that semiconductor devices are superposed in multiple layers in order to achieve high density mounting thereof. A conventionally used superposed type package has been described in for example, Jpn. Pat. Appln. KOKAI Publication No. 9-219490, Jpn. Pat. Appln. KOKAI Publication No. 10-135267 and Jpn. Pat. Appln. KOKAI Publication No. 10-163414. According to the conventional superposed type packages disclosed in these patent applications, thin small outline package (TSOP), tape carrier package (TCP), ball grid array (BAG) and the like are assembled and after that, a plurality of packages are superposed such that external terminals provided preliminarily on the respective packages match with each other. That is, in case of the conventional superposed type packages, superposing process of the respective assembled packages is added to the assembly process of respective packages. Therefore, the number of the processes is increased corresponding to a number of packages to be superposed. In this process, the number of the processes is increased and production cost and material cost are also increased because spacers to be inserted between the respective superposed packages and the like are used, which is a problem to be solved.
In addition to the above-described problem, there is such a problem that a sufficient reliability cannot be secured in operation because a layer boundary is generated in each package when respective packages are superposed. Further, there is also such a problem that a sufficient reliability cannot be secured in terms of mechanical strength. The reason is that the mechanical strength of superposed packages depends on only the strength of electrical connecting portion and therefore the mechanical strength is low. Alternatively, because in conventional example described in the Jpn. Pat. Appln. KOKAI Publication No. 10-163414, Jpn. Pat. Appln. KOKAI Publication No. 10-135267 and the like, the semiconductor device has a float structure, their mechanical strength is low.
Further, the conventional method is not suitable for manufacturing a thin superposed package suitable for a thin semiconductor chip having a thickness of about 30 to 200 &mgr;m for development of a semiconductor device in which high density and thinning of the package have been accelerated so that its application field has been expanded to for example, IC card and portable telephone. Further, the conventional thin package has a problem in terms of adaptability because it is lack of flexibility when it is used as such an elastic medium as IC card.
BRIEF SUMMARY OF THE INVENTION
The present invention has been achieved in view of the above-described problem, and therefore, an object of the invention is to provide a thin semiconductor device using an superposed package having an excellent airproof and elasticity which can be manufactured easily and a manufacturing method therefor.
According to a first aspect of the present invention, there is provided a semiconductor device including a superposed structure formed by superposing a plurality of superposed substrates each comprised of a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, wherein the wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in the wiring printed substrate in such a manner that the contact electrodes are buried in the via holes, and has a plurality of wiring conductors electrically connected to the contact electrodes, the semiconductor element loaded on the wiring printed substrate is electrically connected to the wiring conductors provided on the wiring printed substrate, the conductive-via provided insulating substrate has a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on the wiring printed substrate and a plurality of contact electrodes formed in a plurality of via holes formed in the conductive-via provided insulating substrate in such a manner that the contact holes are buried in the via holes, the conductive-via provided insulating substrate and the wiring printed substrate are superposed in such a manner that the contact electrodes in the conductive-via provided insulating substrate and the contact electrodes in the wiring printed substrate are electrically connected to each other and in such a manner that the semiconductor element loaded on the wiring printed substrate is accommodated in the chip cavity in the conductive-via provided insulating substrate so as to constitute a superposed substrate.
In the semiconductor device according to the first aspect of the present invention, the semiconductor element may be substantially 30 to 200 &mgr;m in thickness.
In the semiconductor device according to the first aspect of the present invention, a space for absorbing a stress may be formed between the chip cavity of the inner conductive-via provided insulating substrate of the superposed substrate and the semiconductor element accommodated in the chip cavity. The space may filled with flexible adhesive agent.
In the semiconductor device according to the first aspect of the present invention, the semiconductor device may further comprise a lower, outer conductive-via provided insulating substrate which is superposed on the wiring printed substrate of an lowermost superposed substrate, the outer conductive-via provided insulating substrate having a plurality of contact electrodes formed in a plurality of via holes formed in the outer conductive-via provided insulating substrate in such a manner that the contact electrodes are buried in the via holes, an upper surface of the lower conductive-via provided insulating substrate being in contact with the wiring printed substrate of the lowermost superposed substrate in such a manner that the plurality of contact electrodes of the lower conductive-via provided insulating substrate are electrically connected to the plurality of contact electrodes in the wiring printed substrate of the lowermost superposed substrate and a lower surface of the lower conductive-via provided insulating substrate having a plurality of external terminals connected to the plurality of contact electrodes formed in the plurality of the holes in the lower conductive-via provided insulating substrate. A space for absorbing a stress may be formed between the chip cavity of the inner conductive-via provided insulating substrate of the superposed substrate and the semiconductor element accommodated in the chip cavity. The space may be filled with flexible adhesive agent.
According to a second aspect of the present invention, there is provided a semiconductor device including a superposed structure formed by superposing a plurality of superposed substrates each comprised of a wiring printed substrate loaded with a semiconductor element and an inner conductive-via provided insulating substrate, and including an upper, outer conductive-via provided insulating substrate which is superposed on the inner conductive-via provided insulating substrate of an uppermost superposed substrate and has a plurality of contact electrodes formed in a plurality of via holes formed in the upper conductive-via provided insulating substrate in such a manner that the contact electrodes are buried in the via holes, wherein the wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes formed in the wiring printed substrate in such a manner that the contact electrodes are buried in the via holes and a plurality of wiring conductors electrically connected to the con
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Williams Alexander O.
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