Superheterodyne circuit having variable bandwidth and center fre

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

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455316, H04B 126

Patent

active

044792573

ABSTRACT:
The invention relates to a superheterodyne circuit characterized by comprising a first mixer converting a received signal into the first intermediate frequency, a second mixer converting the first intermediate frequency into a second intermediate frequency, and a product detection stage demodulating the second intermediate frequency to an audio frequency, by having a constitution wherein the local oscillation of the first mixer is input from a VCO for which a PLL circuit is used, wherein the local oscillation of the second mixer is an output obtained by mixing the frequency of a second oscillator with that of a third oscillator in a fourth mixer, wherein the second oscillator combined with the frequency of the VFO in the sixth mixer, alone or in further combination with the frequency of the output of a BFO input via to the product detection stage is the frequency of the third oscillator or an output obtained by mixing the frequency of the third oscillator with a frequency obtained through the frequency division or multiplication of the frequency of the first oscillator in a fifth mixer, and wherein the output of the second oscillator is input to the fourth mixer and, at the same time, a frequency obtained by mixing said output with the output from a VFO in a sixth mixer is directly input to a third mixer of the PLL circuit, or an output obtained by mixing said frequency with the frequency of the first oscillator or with a frequency obtained through the multiplication or frequency division of the frequency of the first oscillator in a seventh mixer is input to said third mixer, and by conducting a variation of the total bandwidth of an intermediate-frequency stage and a shift of the center frequency by setting a reception band determined by the relationship between the set frequency-division ratio of a programmable frequency divider in the PLL circuit and the frequency of the first oscillator input a seventh mixer or a frequency obtained through the multiplication or frequency division of said frequency, by tuning a received frequency determined by the frequency of the VFO, and by varying the frequency of the second or third oscillator or by simultaneously varying the frequencies of the second and third oscillators.

REFERENCES:
patent: 2998517 (1961-08-01), Beckerich
patent: 3008043 (1961-11-01), Caulk
patent: 3372339 (1968-03-01), Harrison et al.
patent: 4152669 (1979-05-01), Igarashi
patent: 4198604 (1980-04-01), Holdaway
patent: 4211975 (1980-07-01), Kuroda
patent: 4259644 (1981-03-01), Iimura
patent: 4262361 (1981-04-01), Hauer
patent: 4267605 (1979-02-01), Matsuzawa et al.

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