Compositions – Electrically conductive or emissive compositions – Metal compound containing
Reexamination Certificate
2001-10-30
2004-04-13
Einsmann, Margaret (Department: 1751)
Compositions
Electrically conductive or emissive compositions
Metal compound containing
C252S519150, C252S521100, C505S234000, C505S125000, C505S126000, C505S190000, C505S191000, C505S193000, C423S604000, C423S583000
Reexamination Certificate
active
06719924
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-333578, filed Oct. 31, 2000.
BACKGROUND OF THE INVENTION
The present invention relates to a superconducting device and a method of manufacturing the same, particularly, to a superconducting device using an oxide superconductor and a method of manufacturing the same.
It is expected that an oxide superconductor will be utilized in a technical field requiring a high speed operation such as a super-high speed logic arithmetic device or a communication infrastructure. For realizing the utilization of the oxide superconductor, it is said to be of a high priority to establish at an early date a method of manufacturing a Josephson device that is a basic constituting element.
Josephson devices of a laminated type, a ramp edge type, a grain boundary junction type, and a step edge type are known to the art. Each of these Josephson devices is constructed such that a plurality of oxide thin films including a superconductor layer are laminated one upon the other. In the manufacturing process of the Josephson device, after the formation of one or some of the oxide thin films, etching and annealing processes are applied to the resultant structure. As a result, a non-superconductor layer is formed to constitute an interface between a first superconductor layer and a second superconductor layer. Alternatively, defects or dislocations are introduced between the first superconductor layer and the second superconductor layer so as to form an interface.
The construction of the interface highly influences the characteristics of the Josephson device that is finally obtained. Therefore, it is necessary to control with a high accuracy the defects and the dislocation density in the interface. However, the prior art gives rise to the following problem in conjunction with such a process. The problem will now be described, with the forming process of a ramp edge type junction, which is a typical type of junction, taken as an example.
In the forming process of a ramp edge type junction, which does not use a ground plane, in the first step, a superconductor layer used as a base electrode and an insulation layer are successively formed on a substrate so as to obtain a two-layer film. The substrate is generally made of, for example, SrTiO
3
, MgO, La—Sr—Al—Ta—O oxide, NdGaO
3
, LaAlO
3
, or YSZ (Yttrium Stabilized Zirconia). On the other hand, each of the base electrode and a counter electrode referred to herein later is made of, for example, Y—Ba—Cu—O oxide, Nb—Ba—Cu—O oxide, Bi—Sr—Ca—Cu—O oxide, Ti—Ba—Cu—O oxide or (Ba, K)BiO
3
oxide. In this case, the base electrode is made of YB
2
Cu
3
O
7
or NdBa
2
Cu
3
O
7
.
In a second step, a resist pattern is formed on the insulation layer by using a photolithography technique, followed by patterning the insulation layer by an ion milling method or a wet etching method, with the resist pattern used as a mask. As a result, the base electrode is partly exposed to the outside. In this step, a change in structure such as deviation from the inherent composition and change into the amorphous structure takes place in the exposed surface region of the base electrode. Where, for example, the base electrode is made of YBa
2
Cu
3
O
7
, the composition analysis using an XPS indicates that a layer prominently rich in Y is formed in a thickness of about 2 nm in the exposed surface of the base electrode. It is known to the art that the particular layer is amorphous.
Then, in a third step, a high temperature annealing treatment is applied to the two-layer film partially exposing the base electrode to the outside under vacuum or under an oxygen atmosphere. By this heat treatment, the exposed surface region of the base electrode is changed into a layer differing from the inherent structure so as to act as a barrier layer, or forms dislocations or defects in the base electrode and a counter electrode formed in the subsequent step so as to produce the effect of exhibiting the Josephson characteristics. For example, where the base electrode is made of YBa
2
Cu
3
O
7
, the component analysis using an XPS and the structure analysis using an electron microscope indicate that the exposed surface region of the base electrode after the heat treatment noted above contains Y, Ba, Cu and oxygen atoms and that there are a case where a crystal phase of an oxide having a thickness of about 1 nanometer to about several nanometers is grown, and another case where a crystal phase is not present and lattice defects and dislocations are observed in a high density over the entire interface.
In a fourth step, a superconductor layer used as a counter electrode is formed on the two-layer film after the heat treatment. The counter electrode is made of, for example, YBa
2
Cu
3
O
7
. The basic manufacturing process of the Josephson device is finished by the fourth step. However, in order to form the electrode with a high stability, employed are the step of forming a Au layer on the counter electrode and the step of processing the counter electrode into an optional shape.
The manufacturing process described above is directed to a ramp edge type device, and a similar process is employed for the manufacture of the Josephson device of another type such as a laminated type. Also, the manufacturing process described above is directed to the case where the ground plane is not used. However, a process substantially equal to the manufacturing process described above is performed on an insulation film formed on the ground plane.
In order to form a super-high speed logic circuit by using a superconducting device, it is absolutely necessary to make optimum both the critical current (I
c
) value of the junction and the inductance (L
c
) of the wiring portion, which are basic parameters for describing characteristics of the device. When it comes to, for example, the ramp edge type junction, which is a typical device type, it is desirable for I
c
to be about 1 mA and for L
c
to be about 0.7×10
−12
H or less, in the case where the base electrode has a thickness of 200 nm and a junction width of 4 &mgr;m.
Where YBa
2
Cu
3
O
7
or NdBa
2
Cu
3
O
7
is used as a material of the base electrode and YBa
2
Cu
3
O
7
is used as a material of the counter electrode, it was customary to set the temperature for the annealing treatment at a level substantially equal to the substrate temperature in the step of forming the counter electrode. Also, where YBa
2
Cu
3
O
7
is used as a material of the counter electrode, it is necessary to allow the base electrode to have the (001) orientation in order to lower the L
s
value and to manufacture an element having good surface properties. It is generally known in this connection that YBa
2
Cu
3
O
7
forms the (001) orientation only at a temperatures of 750° C. or higher, and that YBa
2
Cu
3
O
7
forms mainly the (100) orientation at a temperature lower than 750° C. Under the circumstances, where the substrate temperature is set at a high level at which the (001) orientation can be achieved, the annealing temperature is rendered excessively high, with the result that the I
c
value deviates from the desired value and the flux flow-like characteristics are observed in many cases.
Also, it is known to the art that the I
c
value is generally lowered in the case where the annealing temperature and the substrate temperature are lowered, provided that the other conditions are the same. It follows that it is possible to lower the I
c
value to a desired level by utilizing the particular phenomenon, i.e., by lowering the substrate temperature, in the annealing step and in the step of forming the counter electrode. However, the particular method causes a large amount of the (100) orientation to be present together in the counter electrode. As a result, a lowering of the critical current (J
c
) of the wiring portion, which causes the elevation of the L
s
value, occurs so as to adversely affect the high speed operation of the device.
As d
Nagano Toshihiko
Yoshida Jiro
Einsmann Margaret
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Vijayakumar Kallambella
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