Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Reexamination Certificate
2007-09-11
2007-09-11
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
C341S143000
Reexamination Certificate
active
11524205
ABSTRACT:
A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.
REFERENCES:
patent: 4039856 (1977-08-01), Schlig
patent: 4136290 (1979-01-01), Davidson et al.
patent: 4365317 (1982-12-01), Gheewala
patent: 5012243 (1991-04-01), Lee
patent: 5124583 (1992-06-01), Hatano et al.
patent: 5191236 (1993-03-01), Ruby
patent: 5398030 (1995-03-01), Sandell
patent: 5610857 (1997-03-01), Nandakumar
patent: 5798722 (1998-08-01), Przybysz et al.
patent: 5818373 (1998-10-01), Semenov et al.
patent: 6242939 (2001-06-01), Nagasawa et al.
patent: 6885325 (2005-04-01), Omelyanchouk et al.
patent: 7038604 (2006-05-01), Hirano et al.
patent: 64-16020 (1989-01-01), None
H. Suzuki, et al.: “Applications of Synchronized Switching in Series-Parallel-Connected Josephson Junctions”; IEEE Transactions on Electron Devices, vol. 37, No. 11, Nov. 1990, pp. 2399-2405.
H. Suzuki, et al.: “Josephson semiconductor interface circuit”; Cryogenics, vol. 30, Dec. 1990, pp. 1005-1008.
J. X. Przybysz, et al.: Interface Circuits for Input and Output of Gigabit per Second Data:, 5thInternational Superconductive Electronics Conference (ISEC '95); Sep. 18-21, 1995, pp. 304-306.
J. X. Przybysz, et al.: “Interface Circutits for Chip-to-chip Data Transfer at GHz Rates”; IEEE Transactions on Applied Superconductivity, vol. 7, No. 2, Jun. 1997, pp. 2657-2660.
D. L. Miller, et al.; “A Josephson Sigma-Delta Analog-to-Digital Converter Using a High-Jc Process”; 8thInternational Supercondictive Electronics Conference (ISEC '01), Jun. 2001, pp. 123-124.
K. K. Likharev, et al.: “RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems”, IEEE transactions on Applied Superconductivity, vol. 1, No. 1, Mar. 1991, pp. 3-28.
Suzuki Hideo
Tanabe Keiichi
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
International Superconductivity Technology Center, The Juridical
Jean-Pierre Peguy
LandOfFree
Superconducting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Superconducting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Superconducting circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3730672