Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2003-01-09
2004-06-01
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S737000, C257S738000, C257S780000, C257S784000, C257S787000, C257S774000
Reexamination Certificate
active
06744125
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for the packaging of Ball Grid Array semiconductor devices.
(2) Description of the Prior Art
Semiconductor devices have since the inception of the semiconductor technology been improved in device performance by packaging more function per package. Not only is the functional capability of a semiconductor device package increased, concurrently the size of the package in which the semiconductor devices are mounted continues to be decreased.
The process of packaging semiconductor devices typically starts with a substrate that is ceramic or plastic based, the devices are mounted on the surface of the substrate while layers of interconnect lines and vias are formed that connect the devices to its surrounding circuitry. Many different approaches are known and have been used for the mounting and interconnecting of multiple semiconductor devices, such as Dual-In-Line packages (DIP), Pin Grid Arrays (PGA), Plastic Leaded Chip Carriers (PLCC) and Quad Flat Packages (QFP). Multi-layer structures have further been used to connect physically closely spaced integrated circuits with each other. Using these techniques, a single substrate serves as an interconnect medium, multiple chips are connected to the interconnect medium forming a device package with high packaging density and dense chip wiring. The chip wiring contains layers of interconnect metal that are interconnected with interconnect vias, layers of dielectric (such as polyimide) or insulating layers separate metal layers that make up the interconnect network and the vias and contact points that establish connections between the interconnect networks.
The Quad Flat Package (QFP) has been created to achieve high pin count integrated packages with various pin configurations. The pin Input/Output (I/O) connections for these packages are typically established by closely spaced leads distributed along the four edges of the flat package. This limits the I/O count of the packages and therefore the usefulness of the QFP. The Ball Grid Array (BGA) package has been created whereby the I/O connects for the package are distributed around the periphery of the package and over the complete bottom of the package. The BGA package can therefore support more I/O points and provides a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
Another packaging concept is realized with the use of so-called flip chips. The flip chip is a semiconductor device that has conductive layers formed on its top surface, external electrical interconnects can be made to these conductive layers by wire bonding selected points of the conductive layers to surrounding circuitry or interconnect lines. The top surface of the flip chip is further provided with so-called solder bumps. At the time of assembly of the flip chip, the chip is turned over (flipped over) so that the solder bumps are now facing downwards and toward the circuit board, typically a printed circuit board, on which the flip chip is to be mounted.
It is clear from the above that a method and package that can be used to package a semiconductor device with high reliability, low packaging cost and a small package size offers considerable competitive advantages in the semiconductor industry. The invention addresses such a package.
U.S. Pat. No. 6,103,550 (Camenforte) shows a molded tape support for a molded circuit package prior to dicing.
U.S. Pat. No. 6,114,760 (Kim et al.) shows a package/method with cavity down, print screening and wire bonding.
U.S. Pat. No. 6,034,427 (Lan et al.) shows package/method with Cu foil, cavity down, print screening and wire bonding.
U.S. Pat. No. 5,696,666 (Miles et al.), U.S. Pat. No. 5,620,928 (Lee et al.), U.S. Pat. No. 5,583,377 (Higgins, III), U.S. Pat. No. 5,986,340 (Mostafazadeh et al.) U.S. Pat. No. 6,020,637 (Karnezos) and U.S. Pat. No. 5,943,212 (Horiuchi et al.) show related patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method and package for packaging semiconductor devices those results in a very thin Ball Grid Array package.
In accordance with the objectives of the invention a new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention an adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil. After this the processing for two embodiments of the invention again commonly proceeds with providing a black ink topping, performing an ink and post mold cure, attaching solder balls to the substrate, providing laser markings on the black ink topping, singulation of the die, inspection and testing after which the devices are packed and shipped as completed devices.
REFERENCES:
patent: 5583377 (1996-12-01), Higgins, III
patent: 5620928 (1997-04-01), Lee et al.
patent: 5696666 (1997-12-01), Miles et al.
patent: 5943212 (1999-08-01), Horiuchi et al.
patent: 5986340 (1999-11-01), Mostafazadeh et al.
patent: 6020637 (2000-02-01), Karnezos
patent: 6034427 (2000-03-01), Lan et al.
patent: 6103550 (2000-08-01), Camenforte et al.
patent: 6114760 (2000-09-01), Kim et al.
Camenforte Raymundo M.
Chow Seng Guan
Merilo Dioscoro A.
Huynh Andy
Ishimaru Mikio
Nelms David
St. Assembly Test Services Ltd.
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