Super self-aligned bipolar transistor and method for...

Details Super self-aligned bipolar transistor and method for... Super self-aligned bipolar transistor and method for...

1998-08-21

2002-01-08

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S511000, C257S616000

Reexamination Certificate

active

06337494

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a super self-aligned heterojunction bipolar transistor and method for manufacturing thereof using a Si/SiGe heterojunction base layer.
2. Description of Prior Art
In general, even if the prior art element has an improved operating speed in proportion to miniaturization of a homojunction bipolar transistor, since, to accomplish this, impurity concentration between emitter and base are increased, enhancement of characteristics thereof based on a structure of such element is a difficult task. A heterojunction bipolar transistor to cope with the above disadvantage has been proposed.
Such a heterojunction bipolar transistor has a characteristic that energy bandgap of an emitter is larger than that of a base. For this reason, utilization of the heterojunction bipolar transistor showed an improvement in the performance of the element and various design effects in comparison to the homojunction bipolar transistor. In addition, in the manufacturing process associated with the homojunction bipolar transistor previously described, a method of decreasing the energy bandgap by adding germanium to a base layer composed of silicon has been developed.
As a conventional homojunction silicon bipolar transistor, the prior art heterojunction bipolar transistors utilize a polysilicon thin film as both a base electrode and an impurity diffusion source for the emitter. Thus, using Ge instead of Si on the base layer, a difference between an energy bandgap of the emitter and that of the base is incurred to increase emitter implantation efficiency, then the base is grown to a high doping concentration ultra-thin film, thereby enhancing a current gain and a switching speed of element.
Recently, in order to optimize and miniaturize the structure of the element, various methods have been used to minimize several parasitic components such as a base resistance at an active region of the element and parasitic capacity between a collector and a base.
Examples of such various methods include a trench isolation, a local oxidation of silicon (“LOCOS”), a selective epitaxial growth(“SEG”) of a SiGe thin film, and a selective epitaxial growth of a Si emitter and so on.
Using the above methods, a super self-aligned Si/SiGe heterojunction bipolar transistor is being developed, which is self-aligned between base and emitter to reduce a base parasitic resistance, or self-aligned both between base and emitter, and between collector and base.
The LOCOS has a disadvantage in that since a bird's beak is horizontally formed as much as the thickness of silicon thermal oxidation film which is vertically formed, there is a limit in geometrically reducing the transistor.
There are shown in
FIG. 1
an exemplary super self-aligned Si/SiGe heterojunction bipolar transistor which is directed to using the SEG method without using the LOCOS method.
Referring now to
FIG. 1
, an n
+
buried silicon collector layer (
1
-
2
), which has a high doping concentration, is first formed on a p-type silicon substrate (
1
-
1
), and an n− silicon collector layer (
1
-
3
), which has a low doping concentration, is then grown on the buried collector layer (
1
-
2
).
Subsequently, a collector junction portion (
1
-
4
) is formed by implanting an n-type impurity ion thereon, and then a trench to isolate between elements is formed by a dry etching method, and, in turn, filling therein with Boron Phosphorous Silica Glass(“BPSG”) insulating thin film (
1
-
5
) made of boron and phosphorous. The BPSG insulating thin film (
1
-
5
) is then flattened under a high pressure.
In an ensuing step, an insulating film (
1
-
6
), a P
+
polysilicon film (
1
-
7
), an insulating film (
1
-
8
) and a side-wall insulating film (
1
-
9
) are formed by depositing and etching methods as shown in
FIG. 1
, and an n-type collector region (
1
-
10
) for enhancing characteristics of elements in a high current region is then formed by selective ion implantation to only an active region of the element.
In a subsequent step, a SiGe base layer (
1
-
11
) is selectively grown on only an exposed portion in the collector region (
1
-
10
) and the polysilicon film (
1
-
7
), through the use of gas source molecular beam technique, and then a polysilicon film (
1
-
12
) is selectively grown on the remaining space, thereby accomplishing a junction between the polysilicon film (
1
-
7
) for a base electrode and the SiGe base layer (
1
-
11
).
Accordingly, self-alignment between the collector and the base can be performed, since a parasitic capacity region formed between the collector and the base is not defined as a photoresist and is limited only to a portion of a polysilicon thin film (
1
-
12
).
Since, however, the parasitic capacity region defined by the polysilicon thin film (
1
-
12
) is determined from a horizontal wet etching for the insulating film (
1
-
6
), resulting in the degradation of efficiency of process in terms of uniformity and reproduction aspects, thus entailing the fatal degradation of the performance of element.
In addition, the prior art method has a disadvantage that since the low speed selective epitaxial growth method is applied two times during the growth of the SiGe base layer (
1
-
11
) and the polysilicon thin film (
1
-
12
), and two thin films for example, the SiGe base (
1
-
11
) and the polysilicon (
1
-
12
), are used during the growth process thereof, resulting in a complicated manufacturing process, and further even if the polysilicon thin film (
1
-
12
) is slightly grown on the base layer (
1
-
11
), it is possible to cause the fatal degradation of element performance, thereby making it difficult to control the process thereof. Thus, with the prior art method it is difficult to accomplish an effective manufacturing process and a simplified processing step.
Furthermore, as shown in
FIG. 1
, the prior art method has a shortcoming in that a trench structure for isolating between elements should be deeply formed so as to prevent the collector junction portion (
1
-
4
) from contacting between elements via the n
−
collector thin film (
1
-
3
) on the n
+
buried Si collector layer (
1
-
2
) formed at the entire surface of a substrate, resulting in a larger space requirement to be filled with the insulating thin film (
1
-
5
), thus entailing a bulkier element.
Turning now to
FIG. 2
, there is presented a cross-sectional view of a Si/SiGe heterojunction bipolar element manufactured by another method previously described, after the growth of a base thin film. In the prior art exemplary shown in
FIG. 2
, both of the base and the collector thin films are grown through the use of the SEG method in contrast with the trench structure previously described, to thereby accomplish a simplified and an integrated manufacturing process.
As shown in
FIG. 2
, an n
+
-type collector (
2
-
2
) is first formed on a p-type substrate (
2
-
1
), and then an insulating thin film (
2
-
3
) and a polysilicon thin film (
2
-
4
) for a base electrode are sequentially deposited thereon. Thereafter, a base electrode region is defined by a photoresist mask and etching of the polysilicon thin film (
2
-
4
).
After the above step, an insulating thin film (
2
-
5
) is deposited thereon, and then the photoresist mask, the insulating thin film (
2
-
5
), the polysilicon thin film (
2
-
4
) and the insulating thin film (
2
-
3
) are defined as an active region by etching process.
Subsequently, an n-type silicon layer (
2
-
6
) for a collector, a SiGe layer (
2
-
7
) for a base, and a silicon layer (
2
-
8
) for an emitter are sequentially grown through the application of impurity thereon.
During the growth of the layers, (
2
-
6
), (
2
-
7
), and (
2
-
8
), as shown in
FIG. 2
, a polycrystalline or an amorphous silicon thin films, (
2
-
6
-
1
), (
2
-
7
-
1
) and (
2
-
8
-
1
), are formed at each side thereof, respectively. Thereafter, a silicide thin film (
2
-
9
) for a collector metal junction is formed, and a metal electrode (
2
-
10
) is then depos

Affiliated with

Also associated with

Rating

Super self-aligned bipolar transistor and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Super self-aligned bipolar transistor and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Super self-aligned bipolar transistor and method for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2853371