Super-regenerative receiver including phase-locked loop

Details Super-regenerative receiver including phase-locked loop Super-regenerative receiver including phase-locked loop

2007-05-08

2007-05-08

Vuong, Quochien B. (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Frequency or phase modulation

C455S255000, C455S256000, C455S259000, C455S250100, C455S296000

Reexamination Certificate

active

10405269

ABSTRACT:
An improved low-cost super-regenerative receiver includes sampling phase-locked loop. Phase sampling is controlled by the quench signal (264). In the preferred embodiment, logic state HIGH to logic state LOW transition of the quench signal (264) defines the timing for the event of sampling. While the quench signal (264) is in logic state HIGH, a quenched oscillator is being turned ON and the oscillation amplitude builds-up until a steady-state level is reached. When the oscillator is turned OFF, effective quality factor of an electronically tunable resonator (206) is reduced, by increasing losses in the circuit, thus to ensure aperiodic (non-oscillatory) decay. The resonator's charge—an energy stored on internal reactive components of the resonator (206), which existed at the instant of turning the oscillations OFF, is transferred during precisely defined period of time to the charge holding capacitor (404) of a charge transfer circuit (216). Charge is stored on the charge holding capacitor (404), which is also part of a loop filter, until the described here charge transfer cycle is repeated again. A frequency control signal (268) at the output of the loop filter sets the frequency of the oscillation for the duration of the succeeding oscillator ON time.

REFERENCES:
patent: 4995053 (1991-02-01), Simpson et al.
patent: 5363415 (1994-11-01), Iwasaki
patent: 5621756 (1997-04-01), Bush et al.
patent: 6035002 (2000-03-01), Schleifer
patent: 6668165 (2003-12-01), Cloutier
patent: 6864756 (2005-03-01), Peng
patent: 6904101 (2005-06-01), Tang
Joehl; et al., “A Low-Power I-GHZ Super-Regenerative Transceiver With Time-Shared PLL Control”, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001, pp. 1025-1031.

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