Super high-speed sequential column decoder

Details Super high-speed sequential column decoder Super high-speed sequential column decoder

1998-12-16

1999-11-09

Phan, Trong

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365236, 36518905, G11C 800

Patent

active

059827033

ABSTRACT:
A super high-speed sequential column decoder generates a high-speed successive output signals by using a pipe lining method and is operated irrespective of an applied speed of an external input clock signal, in a burst operation of a clock synchronous memory. The super high-speed sequential column decoder includes: a column address decoding portion which receives column address signals, decodes the column address signals, and transmits decoding signals to input terminals of a driving portion; and a pipeline-type column counter portion which has as many unit counters as burst-lengths, wherein, the unit counters receives the decoding signal as an input and sequentially generating column decoder signals. As a result, the super high-speed sequential column decoder freely adjusts a time delay, reduces a pulse width of the predecoding signals of an external column address, and thus drives the sequential column decoder signals at a high-speed frequency. In addition, the super high-speed sequential column decoder is operated irrespective of a speed of an external clock signal, thereby increasing the effectiveness of use.

REFERENCES:
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5703830 (1997-12-01), Yasuhiro
patent: 5751656 (1998-05-01), Schaefer
patent: 5777943 (1998-07-01), Kim et al.
patent: 5777945 (1998-07-01), Sim et al.
patent: 5848024 (1998-12-01), Cho

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