Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-06-02
2002-03-19
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06360242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a summing circuit used in a digital system.
2. Description of the Related Art
In a digital signal processing system, an input digital signal is generally subjected to a filtering process using a convolution integration. The convolution integration is carried out through summation. Therefore, it is desired to execute a great deal of calculation in a higher speed and a higher precision. The summing circuit contributes to improvement in the processing speed and the calculation precision in the above-mentioned product and summation calculation, in addition to addition of a plurality of digital data.
FIG. 1
shows a typical summing circuit as a first conventional example. The first conventional example of the summing circuit is composed of a shifter
701
, an adder
703
and a RAM
705
. The shifter
701
shifts a k-bit input data into the LSB direction of the input data to output as a (m−n)-bit data. The adder
703
adds the (m−n) data and a previous summation data to output a new current m-bit summation data. The RAM
705
stores the summation data temporarily.
Referring to
FIG. 1
, a plurality of k-bit positive data are summed. While the summing result is stored in the RAM
705
, the summation is carried out p times and an m-bit summation value is obtained. In this case, for the purpose of avoiding the cutting-off of a part of data without any overflow, it is necessary to satisfy the relation of m=k+n in (n−1)<log(p)≦n (the base of the logarithm is 2). In this case, the value m increases as the value n increases. As a result, the capacity of the RAM
705
necessary to store the summation also increases.
Next,
FIG. 2
shows a summing circuit of the product and summation unit in Japanese Laid Open Patent Application (JP-A-Heisei 9-62653) as a second conventional example. Referring to
FIG. 2
, the second conventional example of the summing circuit is composed of a first adder
801
, a second adder
803
, a third adder
805
, a register
809
and a multiplexer
807
. The first adder
801
is provided for a calculation to a lower 8 bits of an output of the summing circuit. The second adder
803
is provided for a calculation to a middle 8 bits of the output of the summing circuit. The third adder
805
is provided for a calculation to an upper 8 bits of the output of the summing circuit. The register
809
stores the summing result temporarily. The multiplexer
807
outputs the calculating result of the summing circuit based on a signal supplied to a third input terminal
814
.
The operation of the above summing circuit will be described. Referring to
FIG. 2
, a 8-bit data is supplied to a second input terminal
813
and is converted into a digit shift data
816
indicative of a digit shift quantity by a data converter
818
. A barrel shifter
811
shifts a data signal from a first input terminal
812
in digit based on the digit shift data
816
to output a 16-bit data. Thus, a multiplying process is executed. Subsequently, the lower 8-bit data of the 16-bit data from the barrel shifter
811
is supplied to the first adder
801
, and the upper 8-bit data is supplied to the second adder
803
. Thus, the summing process is started.
The first adder
801
adds the lower 8-bit data from the barrel shifter
811
and a lower 8-bit data of a 24-bit data from the multiplexer
807
to output an addition result data to the register
809
as the lower 8-bit data of the summing circuit. Also, the first adder
801
outputs a lower carry signal to the register
809
. In this case, the first adder
801
outputs the lower carry signal having the bit state of “1” to the register
809
, when the overflow occurs in the data of the addition result.
The second adder
803
adds the upper 8-bit data of the 16-bit data from the barrel shifter
811
and a middle 8-bit data of the 24-bit data from the multiplexer
807
to output a summation resultant data to the register
809
as the middle 8-bit data of the summing circuit. In this case, the second adder
803
adds “1” to the least significant bit of the summation resultant data, when the lower carry signal is “1”. Also, the second adder
803
outputs the summation resultant data to the register
809
when the carry signal is “
0
”. Also, the second adder
803
outputs a middle carry signal to the register
809
. Further, the second adder
803
outputs a middle carry signal of “1” when the overflow occurs in the summation resultant data.
The third adder
805
adds “1” to the least significant bit of an upper 8-bit data of the 24-bit data from the multiplexer
807
when the middle carry signal is “1”, and outputs the summation resultant data to the register
809
. When the middle carry signal is “0”, the third adder
805
outputs the summation resultant data from the multiplexer
807
to the register
809
just as it is. One of the input terminals of the third adder
805
is grounded such that data of “0” is always inputted to the input terminal.
The register
809
holds the summation resultant data from the first adder
801
, the lower carry signal, the summation resultant data from the second adder
803
, the middle carry signal, and the summation resultant data from the third adder
805
by one period of a clock signal to output to the multiplexer
807
.
The multiplexer
807
selectively outputs one of the data supplied through the third input terminal
814
and the data supplied from the register
809
. That is, the multiplexer
807
outputs the input data of “0” supplied through the third input terminal
814
to another input terminal of the first adder
801
, the carry input terminal of the second adder
803
, another input terminal of the second adder
803
, the carry input terminal of the third adder
805
and another input terminal of third adder
805
in response to the first clock signal. Also, the multiplexer
807
outputs the data supplied from the register
809
to the first, second and third adders in response to the second clock signal and the subsequent, as follows. That is, the multiplexer
807
outputs the summation resultant data supplied from the first adder
801
to the other input terminal of the first adder
801
, the lower carry signal supplied from the first adder
801
to the carry input terminal of the second adder
803
, the summation resultant data supplied from the second adder
803
to the other input terminal of the second adder
803
, the middle carry signal supplied from the second adder
803
to the carry input terminal of the third adder
805
, and the summation resultant data supplied from the third adder
805
to the other input terminal of the third adder
805
.
The above summing circuit is a 24-bit adder composed of three 8-bit adders and one register. The lower carry signal from the first adder
801
and the middle carry signal from the second adder
803
are transmitted to the adders on the side of the upper bits at the time of the next clock, after being held in the register for one period time of the clock signal. In this way, the carry transmission time for the addition is made short so that it is possible to short the summing operation time.
In the first conventional example shown in
FIG. 1
, the relation of m<k+n is attained when the capacity of the RAM, i.e., the data word length is constrained. In order to prevent an overflow, it is necessary to cut off a part of data before the adding operation. The lower bits of each input data are cut off in advance to produce (m−n)-bit data for the adding operation. In this method, when (k+n−m) becomes large, the summation precision is degraded largely.
On the other hand, in the second conventional example shown in
FIG. 2
, the data converter and the barrel shifter are used in the product and summation unit, to prevent an overflow in the summing circuit. However, this function is contained in the function for the multiplying process, and the summing circuit does not have the function as its internal function.
SUMMARY OF
Malzahn David H.
Sughrue & Mion, PLLC
LandOfFree
Summing circuit with high precision does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Summing circuit with high precision, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Summing circuit with high precision will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2834679