Electrical computers: arithmetic processing and calculating – Electrical analog calculating computer – Particular function performed
Reexamination Certificate
1999-11-24
2003-11-11
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical analog calculating computer
Particular function performed
C708S813000
Reexamination Certificate
active
06647406
ABSTRACT:
This patent application claims priority based on a Japanese patent application, H10-333669 filed on Nov. 25, 1998, and H1l-307321 filed on Oct. 28, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sum of product circuit and an inclination detecting apparatus. In particular, the present invention relates to a sum of product circuit and an inclination detecting apparatus that uses said sum of product circuit to calculate the analog multilevel data accurately and at high-speed.
2. Description of the Related Art
When using an analog quantity, a computer usually initially converts an analog quantity to a digital quantity using an A/D converter, and then operates the digital processing. The digital processing is accurate, but the quantity of the data becomes enormous and the steps of process also become large. Therefore, it is difficult to respond in real time, especially if the information processing such as recognition of a specific shape from a two-dimensional picture is processed by a digital circuit.
For example, as a method of detecting a location and a rotation angle of a line existing in a binary picture, there is an image processing method known as a linear Hough conversion. The linear Hough conversion inputs a coordinate value of an active picture element in a binary picture, such as picture element of picture element value “1”. The linear Hough conversion then operates a circular function and a sum of the product operation, then maps the results of the operation on two-dimensional memory. The linear Hough conversion is not sensitive to noise. The linear Hough conversion can detect a rotation angle of a line even if the line is cut halfway or if a plurality of lines are crossed in a complicated pattern. Therefore, the linear Hough conversion is used in various fields such as real time image processing.
FIG. 1
shows a Hough conversion integrated circuit that uses a digital signal processing circuit to process the linear Hough conversion shown above, in real time. The Hough conversion integrated circuit is constituted by a Metal Oxide Semiconductor (MOS), logic circuit, or a logic integrated circuit such as a Transistor Transistor Logic (TTL). The Hough conversion integrated circuit has an address output means
12
, a ROM (Read Only Memory)
16
, and a sum of product circuit
20
. The address output means
12
outputs an active picture element address of a binary picture, input to the address output means
12
sequentially. The ROM
16
stores a circular function table
18
. The sum of product circuit
20
operates the sum of the product operation, based on the address output from the address output means
12
and a circular function read from the circular function table
18
.
The linear Hough conversion integrated circuit further has a two-dimensional memory
24
, a maximum value detecting unit
26
, and an inclination output unit
28
. The two-dimensional memory
24
stores the results of the sum of the product operation. The maximum value detecting unit
26
detects a maximum value from the storing value stored in the two-dimensional memory
24
. The inclination output unit
28
outputs an inclination of an input picture, based on the maximum value which is detected by the maximum value detecting unit
26
.
To operate the Hough conversion shown above using logic circuit, a two step process is required. The first is storing the data from the ROM
16
, which stores the circular function table
18
, and the second is operating the sum of the product operation on digital address data output from the address output means
12
, and a circular function. Furthermore, to operate the sum of the product operation process to an accuracy of for example 8 bit, eight steps of logical multiplication process and eight steps of parallel full adder process are required. The result is, an increase in the circuit delay.
If this Hough conversion circuit is comprised for example of CMOS (Complementary MOS) logic circuit with an 8 bit operation accuracy, approximately 100 transistors are needed in the ROM, which stores the circular function, and 1500 transistors are needed in the sum of the product circuit. Thus, a total of 1600 transistors are needed. It is possible to use a plurality of Hough conversion circuits in parallel to increase the processing speed. In the case of using sixty Hough conversion circuits in parallel, approximately 100,000 transistors are needed. In this case, the whole area of the LSI chip is dominated by the Hough conversion circuit using the present high integration technology. Therefore, the two-dimensional memory and other circuits have to be assembled into other chips so that the. Hough-conversion circuit as a whole becomes a large scale circuit configuration which includes a plurality of chips.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a semiconductor integrated circuit which can increase processing speed, reduce circuit scale, and process data in parallel by introducing MOS analog circuit technology into a Hough conversion operation integrated circuit. This was constituted by a logic integrated circuit in the past. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a sum of product circuit, which adds two input voltages, each of which is multiplied by prescribed coefficients, may comprise a &ngr; MOS transistor which has a drain, a source, and floating gate; a first and second capacitance which connect each of two input voltage to the floating gate by capacity coupling; a resister element which has prescribed resistance; and an output terminal which outputs a voltage generated between the resister element and the &ngr; MOS transistor; wherein a constant voltage is applied between the drain and the source through the resister element.
The resister element may have a MOS transistor. A sum of product circuit may further have a third condenser which connects the floating gate and ground. The &ngr; MOS transistor may be an N channel &ngr; MOS transistor, and the drain may be connected to an electric potential higher than an electric potential of the source. The &ngr; MOS transistor may be a P channel &ngr; MOS transistor, and the source may be connected to an electric potential higher than an electric potential of the drain. A sum of product circuit may further comprise a plurality of &ngr; MOS transistors wherein the resister element and the first and second condenser can be provided independently for each of the plurality of &ngr; MOS transistors.
By equalizing the value of the first capacitance and the second capacitance to the value of sin &thgr; and cos &thgr; at various angles &thgr;, the sum of the product circuit can sum at high speed the products of sin &thgr; and cos &thgr; at various angles &thgr; and the addresses in the x direction and the y direction. Therefore, Hough conversion can be processed at high speed. In this case, a sum of the square of a capacitance of the first condenser and the square of a capacitance of the second condenser becomes equal for each of the plurality of &ngr; MOS transistors.
A sum of product circuit may further comprise a switch which connects the floating gate to ground electric potential. Using this switch, the initial charge of the floating gate can be used repeatedly, so that the tunnel charge stored in the floating gate can be initialized. Therefore, the sum of the product operation can be processed accurately. The switch can be comprised of a CMOS switch or a combination of a resistor and a capacitor.
According to the second aspect of the present invention, an inclination detecting apparatus which detects the inclination of an input picture comprises, an address output means which outputs each address in the x direction and y direction of a plurality of active picture elements included in th
Maruo Kazuyuki
Shibata Tadashi
Advantest Corporation
Mai Tan V.
Rosenthal & Osha L.L.P.
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