Successive comparison analog-to-digital converter

Details Successive comparison analog-to-digital converter Successive comparison analog-to-digital converter

2002-06-12

2003-05-13

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S150000, C341S156000

Reexamination Certificate

active

06563449

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a successive comparison analog-to-digital (A-D) converter. More particularly, the present invention relates to a charge-redistributing type successive comparison A-D converter.
2. Description of Related Art
With recent improvement in digital processing speed, high speed operation is required for an A-D converter serving as an interface between analog and digital signals.
FIG. 4
is a block diagram of the structure of a common successive comparison A-D converter. In the successive comparison A-D converter of
FIG. 4
, a sample-and-hold section
1
samples and holds an analog input, and a voltage comparator
2
compares the analog input with a voltage from a local digital-to-analog (D-A) converter
3
. A latch circuit
4
latches the output of the voltage comparator
2
. A state control circuit
5
controls the output of the local D-A converter
3
based on the output of the voltage comparator
2
. The voltage comparator
2
successively compares the voltages from the MSB (most significant bit). When the voltage comparator
2
completes the voltage comparison to the LSB (least significant bit), the latch circuit
4
outputs a latched digital value.
A charge-redistributing type successive comparison A-D converter is known as an A-D converter capable of obtaining a large number of converted bits with a small size.
FIG. 5
shows the structure of a conventional charge-redistributing type successive comparison A-D converter. The successive comparison A-D converter of
FIG. 5
is a 3-bit A-D converter, and includes a capacitor array
29
, analog switch groups
30
to
32
, a voltage comparator
27
, and a state control circuit
28
. Note that the latch circuit
4
in
FIG. 4
is not shown in FIG.
5
. The capacitor array
29
includes capacitors
11
to
14
. The capacitors
11
to
14
have a capacitance
4
C,
2
C, C, C, respectively, where C is a unit capacitance. The analog switch group
30
connects the capacitor array
29
to an analog input Vin. The analog switch group
30
includes analog switches
15
to
18
. The analog switches
15
to
18
have an on-state resistance R. The analog switch group
31
connects the capacitor array
29
to a higher reference voltage Vrh (in the illustrated example, power supply voltage Vdd). The analog switch group
31
includes analog switches
19
to
22
. The analog switches
19
to
22
have an on-state resistance R. The analog switch group
32
connects the capacitor array
29
to a lower reference voltage Vrl (in the illustrated example, ground voltage GND). The analog switch group
32
includes analog switches
23
to
26
. The analog switches
23
to
26
have an on-state resistance R. The voltage comparator
27
includes an analog switch
33
and an inverter
34
. The state control circuit
28
controls ON/OFF of the analog switches
15
to
26
,
33
.
Hereinafter, operation of the successive comparison A-D converter in
FIG. 5
will be described.
First, the analog switch group
30
and the analog switch
33
are turned ON, and the analog input Vin is sampled and held in the capacitor array
29
. Provided that the inverter
34
has a threshold voltage Vth, charges Q
0
accumulated in the capacitor array
29
are defined by the following equation:
Q
0
=8
C
(
Vth−Vin
)  (1).
The time required for the sample-and-hold operation is determined by a time constant
4
CR of the capacitor
11
and the analog switch
15
.
When the sample-and-hold operation is completed, the analog switches
15
to
18
,
33
are turned OFF, and the accumulated charges Q
0
are stored on the side of the voltage comparator
27
in the capacitor array
29
.
The successive comparison A-D converter then proceeds to operation of comparing the MSB (bit
2
). In this operation, the analog switches
19
,
24
to
26
are turned ON and the charges Q
0
are redistributed to the capacitor array
29
. An input voltage Vx to the inverter
34
is defined by the following equation according to the principle of conservation of charge:
Vx=Vth−
(
Vin−
(½)
Vdd
)  (2).
For Vin>(½)Vdd, the voltage comparator
27
outputs “Hi”, and the MSB is determined as “1”. For Vin<(½)Vdd, the voltage comparator
27
outputs “Low”, and the MSB is determined as “0”.
After the MSB is determined, the successive comparison A-D converter proceeds to operation of comparing the following bit (bit
1
). When the voltage comparison output of the MSB is “Hi”, the analog switches
19
,
20
,
25
,
26
are turned ON. On the other hand, when the voltage comparison output of the MSB is “Low”, the analog switches
23
,
20
,
25
,
26
are turned ON. It is herein assumed that the voltage comparison output of the MSB is “Hi”. In this case, the analog switches
19
,
20
,
25
,
26
are turned ON and the charges Q
0
are redistributed to the capacitor array
29
. An input voltage Vx to the inverter
34
is defined by the following equation according to the principle of conservation of charge:
Vx=Vth−
(
Vin
−(¾)
Vdd
)  (3).
For Vin>(¾)Vdd, the voltage comparator
27
outputs “Hi”, and bit
1
is determined as “1”. For Vin<(¾)Vdd, the voltage comparator
27
outputs “Low”, and bit
1
is determined as “0”.
After bit
1
is determined, the successive comparison A-D converter proceeds to operation of comparing the following bit, LSB (bit
0
). When the voltage comparison output of bit
1
is “Hi”, the analog switches
19
,
20
,
21
,
26
are turned ON. On the other hand, when the voltage comparison output of bit
1
is “Low”, the analog switches
19
,
24
,
21
,
26
are turned ON. It is herein assumed that the voltage comparison output of bit
1
is “Low”. In this case, the analog switches
19
,
24
,
21
,
26
are turned ON and the charges Q
0
are redistributed to the capacitor array
29
. An input voltage Vx to the inverter
34
is defined by the following equation according to the principle of conservation of charge:
Vx=Vth−
(
Vin
−(⅝)
Vdd
)  (4).
For Vin>(⅝)Vdd, the voltage comparator
27
outputs “Hi”, and the LSB is determined as “1”. For Vin<(⅝)Vdd, the voltage comparator
27
outputs “Low”, and bit
1
is determined as “0”.
Charges are redistributed when every bit is determined. The time required for such charge redistribution is equal to that required for the sample-and-hold operation, and determined by a time constant
4
CR of the capacitor
11
and the on-state resistance of the analog switch
19
or
23
.
The successive comparison A-D converter in
FIG. 5
has different time constants
4
CR,
2
CR, CR, CR for the capacitors
11
to
14
of the capacitor array
29
, respectively. For the capacitor
11
, each of the time required to sample and hold the analog input Vin and the time required for charge redistribution is therefore four times that for the capacitor
14
. Accordingly, the A-D converter can operate only at about a quarter of the maximum possible speed. In other words, in the case of an N-bit A-D converter, the operation speed is reduced to at most ½
(N−1)
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a successive comparison A-D converter capable of improving the operation speed.
According to one aspect of the present invention, a successive comparison A-D converter includes a plurality of capacitors, a plurality of first analog switches, a plurality of second analog switches, a plurality of third analog switches, a voltage comparator, and a state controller. The plurality of capacitors have their respective one electrodes connected to each other. Each of the plurality of capacitors has a capacitance weighted with a prescribed weighting factor. The plurality of first analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of first analog switches is connected between the other electrode of a corresponding capacitor and a

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