Successive approximation shift register with reduced latency

Details Successive approximation shift register with reduced latency Successive approximation shift register with reduced latency

1998-06-29

2000-11-28

Young, Brian

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 138

Patent

active

06154163&

ABSTRACT:
A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.

REFERENCES:
patent: 4940981 (1990-07-01), Naylor et al.
patent: 5859608 (1999-01-01), Fucili et al.

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