Successive approximation analog-to-digital converter with...

Details Successive approximation analog-to-digital converter with... Successive approximation analog-to-digital converter with...

2002-11-22

2004-12-07

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S161000, C341S172000

Reexamination Certificate

active

06828927

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to analog-to-digital conversion and in particular to successive approximation A-to-D converters, and is more particularly directed toward a successive approximation A-to-D converter in which the most significant bits of the SAR are pre-loaded with a value nearly equal to the desired result.
BACKGROUND OF THE INVENTION
Successive approximation ADC is the name commonly given to an analog-to-digital conversion process in which digital approximations of the input analog voltage are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower than the input analog value.
The initial value of the SAR is conventionally set to one-half the number that can be represented in the n bits of the SAR. To be more precise, an n-bit register can contain a value of 2
n
−1, but for purposes of successive approximation, the initial value has the most significant bit set and the others cleared, which translates into a value of 2
n
/2. If this comparison reveals that the digital approximation is indeed lower than the input voltage, the bit that was initially set remains set, the bit of next greater significance is also set, and another trial commences. If on the other hand, the SAR value is greater than the input analog voltage, the bit that was set for that trial is cleared, the bit of next greater significance is set, and another trial commences. It can be appreciated from this example why a successive approximation approach bears such a similarity to a binary search procedure.
Each bit of the SAR is set or cleared based upon a trial, so the conversion process requires only “n” trials to reach completion. SAR-type algorithms achieve conversion in much less time than a ramp-up technique. A ramp-up type of conversion, for example, requires that the input register of the D/A converter “count-up” by increments of 1 until the analog value is reached. Since each increment of the input register requires a trial to determine whether the analog input level has been reached, many trials may have to be performed before a successful conversion is achieved. There are other types of conversion systems that are even faster than SAR ADC, such as pipeline, flash, and half-flash, but these techniques require much more power than the SAR approach, and are thus unsuitable in many applications.
The main difficulty in AID conversion generally is settling time. The digital value that is written to the input register (the SAR register in a successive approximation system) produces an analog output at the D/A converter which must be allowed to settle completely before a comparison is performed in order to guarantee system accuracy.
As noted, a conventional SAR converter consists of only a DAC (digital-to-analog converter), a SAR register, control logic, and a single comparator. To generate an N-bit conversion result, each component of the converter is used (or updated) N times in a series of what are known as bit trials. Since only one comparator is used, the converter linearity is only limited by the accuracy of the DAC. The conversion time is dominated by the settling time of the DAC, which has to settle to system accuracy every bit trial. Since it is now possible to make very accurate DACs, SAR converters can be made to be extremely accurate. They also require very few analog components. However due to the serial way by which the result is derived, they are inherently slow.
Accordingly, a need arises for an ADC that occupies a relatively small amount of valuable integrated circuit real estate, has a high accuracy, and reaches a conversion result rapidly.
SUMMARY OF THE INVENTION
These needs and others are satisfied by the SAR ADC of the present invention. While successive approximation SARs are extremely efficient at moderate throughput rates of up to 1 MHz (megahertz), for example, the large number of clock cycles necessary to implement a single conversion makes it very difficult to implement significantly higher speed converters. Keeping in mind that a conventional SAR converter includes a DAC and an associated SAR register, a way to dramatically reduce the number of clock cycles required is to pre-load the SAR register's most significant bits with a value that makes the DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded.
The value used to pre-load the most significant bits of the SAR can be obtained from a low-resolution, high-speed converter, such as a flash. However, with a binary weighted SAR converter architecture, the accuracy of the high-speed converter must be at least the same as the required accuracy of the whole converter. But if the range of the DAC bits used in the normal SAR part of the conversion is increased, then errors up to a certain magnitude in the high-speed converter can be corrected. The range can be increased by adding what are sometimes known as redundant bits. These redundant bits are extra bits that would not strictly be required if no inaccuracy existed in the high-speed converter.
In accordance with one aspect of the present invention, an improved successive approximation analog-to-digital converter that produces an output digital representation of an input signal to be converted, includes a successive approximation register driving a first digital-to-analog converter, and a comparator to which both the output of the first digital-to-analog converter and the input signal are applied. The improvement comprises a second digital-to-analog converter driven by an analog-to-digital converter, wherein the output of the second digital-to-analog converter is summed with the output of the first digital-to-analog converter prior to being applied to the comparator. Preferably, the analog-to-digital converter driving the second digital-to-analog converter performs a coarse conversion of the input signal to be converted and propagates the coarse conversion result to the second digital-to-analog converter prior to the successive approximation conversion.
In one form of the invention, the analog-to-digital converter driving the second digital-to-analog converter may incorporate, at least in part, a parallel analog-to-digital converter. The parallel analog-to-digital converter may comprise, at least in part, a flash converter or a pipeline converter, for example.
In another form of the invention, the first digital-to-analog converter has an associated full-scale range derived by subtracting negative full-scale value from positive full-scale value, and the full-scale range is constrained to be greater than a value derived by subtracting the weight of an LSB of the first digital-to-analog converter from the weight of an LSB of the second digital-to-analog converter.
In still another form of the invention, the first digital-to-analog converter has a full-scale range at least equal to a value derived by subtracting the weight of an LSB of the first digital-to-analog converter from the weight of an LSB of the second digital-to-analog converter, and adding the magnitudes of the analog-to-digital converter's most positive code transition error plus the magnitude of the analog-to-digital converter's most negative code transition error, such that potential errors introduced by analog-to-digital converter code transition errors are eliminated from the output digital representation. Of course, either of the analog-to-digital converter's most positive or most negative code transition errors may be zero.
Preferably, negative code transition errors are effectively eliminated by shifting all code transitions in a positive direction by an amount at least equal to the magnitude of the largest negative code transition error. Negative code transition errors may be effectively eliminated by shifting comparator thresholds, for example, or by

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