Successive approximation ADC with rounding to vary bit number ou

Details Successive approximation ADC with rounding to vary bit number ou Successive approximation ADC with rounding to vary bit number ou

1995-07-17

1997-06-10

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 100

Patent

active

056380755

ABSTRACT:
An analog/digital (A/D) converter includes a sequential approximation register (SA register) having a plurality of bits for storing the results of conversion in digits and an incrementor having a smaller number of bits than that of the SA register. The incrementor increments a portion of the results of conversion on the basis of the result of conversion of at least one bit in the SA register so as to minimize an error in the A/D conversion of a smaller number of bits than that of the SA register.

REFERENCES:
patent: 4553128 (1985-11-01), Pilost
patent: 4823130 (1989-04-01), Wright et al.
patent: 5262779 (1993-11-01), Sauer et al.

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