Successive approximation A/D converter correcting for charge inj

Details Successive approximation A/D converter correcting for charge inj Successive approximation A/D converter correcting for charge inj

1992-06-02

1993-09-21

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

341165, H03M 138

Patent

active

052472990

ABSTRACT:
In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time. Transmission gate and switch transistor are controlled by a binary control signal "sample/convert" to turn M2 off during a sample time, and to couple the DAC output to the reference input during convert time.

REFERENCES:
patent: 3818246 (1974-06-01), Hellwarth et al.
patent: 4228423 (1980-10-01), Schwerdt
patent: 4947169 (1990-08-01), Smith et al.
patent: 4973975 (1990-11-01), Yamazaki et al.
A. Grebene, Bipolar and MOS Analog Integrated Circuit Design (John Wiley & Sons, Inc., 1984), Chapter 15.

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