Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-01-11
2002-04-30
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06380881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to analog-to-digital converters and, more particularly, to a successive approximation analog-to-digital converter (hereinafter, referred to as a successive approximation A/D converter) capable of error correction. A successive approximation A/D converter is defined as an A/D converter effecting analog-to-digital conversion by determining a binary code bit by bit.
2. Description of the Related Art
A successive approximation A/D converter is well known in the art as an analog-to-digital converter for use in mechanical control such as servo control.
FIG. 12
shows a construction of a 4-bit successive approximation A/D converter according to the related art. Referring to
FIG. 12
, the 4-bit successive approximation A/D converter comprises an analog input terminal
101
, a conversion result output terminal
102
, a sample and hold
103
(hereinafter, referred to as an S/H), a digital-to-analog converter
104
(hereinafter, referred to as a DAC), a ladder resistor (referred to as an SAR)
105
, a 1-bit comparator
106
and a control circuit
107
provided with a latching function. The 1-bit comparator
106
is given its designation because it outputs a 1-bit conversion result to the control circuit
107
in one conversion cycle.
A description will now be given of the operation of each of the converter elements.
The S/H
103
having an input thereof connected to the analog input terminal
101
and an output thereof connected to the 1-bit comparator
106
holds an analog input voltage input via the analog input terminal
101
while the 1-bit comparator
106
is performing a comparison operation. The SAR
105
is comprised of a group of resistors for dividing an externally supplied or internally generated reference voltage in 16 steps (2
4
=16) so as to output a voltage that serves as a reference in a comparison operation (hereinafter, simply referred to as a comparison reference voltage) to the DAC
104
. The DAC
104
outputs to the 1-bit comparator
106
the comparison reference voltage produced by the SAR
105
or a comparison reference voltage produced on the basis of the comparison reference voltage produced by the SAR
105
, in accordance with a control signal supplied from the control circuit
107
. The 1-bit comparator
106
compares the analog input voltage held in the S/H
103
with the comparison reference voltage supplied from the DAC
104
. The 1-bit comparator
106
converts a result of comparison into digital data so as to output the digital data to control circuit
107
. The 1-bit comparator
106
outputs “1” as a conversion result when it is determined that the analog input voltage is higher than the comparison reference voltage and outputs “0” as a conversion result when it is determined that the analog input voltage is lower than the comparison reference voltage. The control circuit
107
latches the 1-bit conversion result output from the 1-bit comparator
206
and determines a voltage to be used as the comparison reference voltage in the subsequent comparison, based on the conversion result. The control circuit
107
outputs the control signal to the DAC
104
so as to set the determined voltage therein. When an entire conversion process is completed, the control circuit
107
outputs a final conversion result based on a 4-bit conversion result to the conversion result output terminal
102
.
FIG. 13
shows a sequence of operations performed by the 4-bit successive approximation A/D converter according to the related art. A vertical scale
108
indicates 16 discrete values that the comparison reference voltage can take. A dotted line
109
indicates the analog input voltage. A solid line
110
indicates the comparison reference voltage subject to comparison with the analog input voltage by the 1-bit comparator
106
. Binary values
111
indicate conversion results output in respective conversion cycles from the 1-bit comparator
106
. Each of two-way arrows
112
indicates a conversion cycle.
A description will now be given of a sequence of a conversion operation.
In a bit
3
conversion cycle, voltage
8
is set by the SAR
105
and the DAC
104
as the comparison reference voltage. The level of voltage
8
is half that of an upper limit of the comparison reference voltage used in digital conversion of the analog input voltage. The 1-bit comparator
106
then compares the voltage
8
with the analog input voltage. Since the analog input voltage is higher in level than voltage
8
, the 1-bit comparator
106
outputs “1” as the conversion result. The control circuit
107
latches the conversion result in the bit
3
conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. If the conversion result in the bit
3
conversion cycle is “1”, voltage
12
is set by the control signal. If the conversion result in the bit
3
conversion cycle is “0”, voltage
4
is set by the control signal. Since, in this case, the conversion result output from the 1-bit comparator
106
is “1”, voltage
12
is set as the comparison reference voltage in the subsequent comparison.
In a bit
2
conversion cycle, voltage
12
is set by the SAR
105
and the DAC
104
as the comparison reference voltage so that the 1-bit comparator
106
compares voltage
12
with the analog input voltage. Since the analog input voltage is higher in level than voltage
12
, the 1-bit comparator
106
outputs “1” as the conversion result. The control circuit
107
latches the conversion result in the bit
2
conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. That is, the control circuit
107
outputs the control signal to the DAC
104
to set the comparison reference voltage to be used in a bit
1
conversion cycle, based on the latched conversion result in the bit
3
conversion cycle and the latched conversion result in the bit
2
conversion cycle. Assuming that the conversion result in the bit
3
conversion cycle is “1”, if the conversion result in the bit
2
conversion cycle is “1”, voltage
14
is set by the control signal; if the conversion result in the bit
2
conversion cycle is “0”, voltage
10
is set by the control signal. Since, in this case, the conversion result in the bit
2
conversion cycle is “1”, voltage
14
is set as the comparison reference voltage to be used in the subsequent comparison.
In the bit
1
conversion cycle, voltage
14
is set by the SAR
105
and the DAC
104
as the comparison reference voltage so that the 1-bit comparator
106
compares voltage
14
with the analog input voltage. Since the analog input voltage is lower in level than voltage
14
, the 1-bit comparator
106
outputs “0”, as the conversion result. The control circuit
107
latches the conversion result in the bit
1
conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. That is, the control circuit
107
outputs the control signal to the DAC
104
to set the comparison reference voltage to be used in bit
0
conversion cycle, based on the latched conversion result in the bit
3
conversion cycle, the latched conversion result in the bit
2
conversion cycle and the latched conversion result in the bit
1
conversion cycle. Assuming that the conversion result in the bit
3
conversion cycle is “1” and the conversion result in the bit
2
conversion cycle is “1”, if the conversion result in the bit
1
conversion cycle is “1”, voltage
15
is set by the control signal; if the conversion result in the bit
1
conversion cycle is “0”, voltage
13
is set by the control signal. Since, in this case, the conversion result in the bit
1
conversion cycle is “0”, voltage
13
is set as the comparison reference voltage to be used in the subsequent comparison.
Finally, in the bit
0
conversion cycle
Harada Hisashi
Miki Takahiro
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