Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1998-11-13
2000-05-23
Fourson, George
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
438433, H01L 21762
Patent
active
060668857
ABSTRACT:
In a semiconductor employing shall trench isolation, a subtrench conductive layer formed before the isolation dielectric is present by implanting dopants into the floor and sidewalls of the shallow trench using a large tilt angle (LTA) implant. The subtrench conductive layer is advantageously used to interconnect what would normally be isolated devices. In lieu of metal or polysilicon interconnects which reside over the isolation dielectric, the subtrench conductive layer is formed entirely within the silicon substrate, and resides beneath and laterally adjacent the isolation dielectric. The conductive layer is formed by implanting ions into the floor and sidewalls of a shallow trench prior to filling the trench with the isolation dielectric. The implantation at specified dosages presents a layer of dopant within the exterior surfaces of the trench sidewalls and floor. Implantation or diffusion of source/drain regions occur after the conductive layer is formed and the isolation dielectric is formed. The source/drain region of a first active area and the source/drain region of a second active area are fashioned so as to intermingle with and be a part of the conductive layer opposing ends. Mutuality of dopants within the source/drain regions interconnected by the conductive layer causes formation of an electrically conductive path across the conductive layer, underneath the isolation dielectric.
REFERENCES:
patent: 3466741 (1969-09-01), Wiesner
patent: 4493740 (1985-01-01), Komeda
patent: 4653177 (1987-03-01), Lebowitz et al.
patent: 4904609 (1990-02-01), Temple
patent: 4918027 (1990-04-01), Fuse et al.
patent: 4980310 (1990-12-01), Matsuda et al.
patent: 4987093 (1991-01-01), Teng et al.
patent: 4994407 (1991-02-01), Custode et al.
patent: 5010025 (1991-04-01), Solomon
patent: 5141882 (1992-08-01), Komori et al.
patent: 5173438 (1992-12-01), Sandhu
patent: 5212111 (1993-05-01), Doan
patent: 5266510 (1993-11-01), Lee
patent: 5342803 (1994-08-01), Shimoji
patent: 5372963 (1994-12-01), Mori
patent: 5378641 (1995-01-01), Cheffings
patent: 5401671 (1995-03-01), Komori et al.
patent: 5405788 (1995-04-01), Manning et al.
patent: 5468677 (1995-11-01), Jun
patent: 5482873 (1996-01-01), Yang
patent: 5529948 (1996-06-01), Lur et al.
patent: 5607881 (1997-03-01), Huang
patent: 5624859 (1997-04-01), Liu et al.
patent: 5767000 (1998-06-01), Fulford, Jr. et al.
Dawson Robert
Fulford Jr. H. Jim
Advanced Micro Devices , Inc.
Daffer Kevin L.
Fourson George
Kowert Robert C.
LandOfFree
Subtrench conductor formed with large tilt angle implant does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Subtrench conductor formed with large tilt angle implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Subtrench conductor formed with large tilt angle implant will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1838994