Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-05-23
1999-02-23
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438221, 438296, 438525, 438524, H01L 2176
Patent
active
058743464
ABSTRACT:
In a semiconductor employing shall trench isolation, a subtrench conductive layer formed before the isolation dielectric is present by implanting dopants into the floor and sidewalls of the shallow trench using a large tilt angle (LTA) implant. The subtrench conductive layer is advantageously used to interconnect what would normally be isolated devices. In lieu of metal or polysilicon interconnects which reside over the isolation dielectric, the subtrench conductive layer is formed entirely within the silicon substrate, and resides beneath and laterally adjacent the isolation dielectric. The conductive layer is formed by implanting ions into the floor and sidewalls of a shallow trench prior to filling the trench with the isolation dielectric. The implantation at specified dosages presents a layer of dopant within the exterior surfaces of the trench sidewalls and floor. Implantation or diffusion of source/drain regions occur after the conductive layer is formed and the isolation dielectric is formed. The source/drain region of a first active area and the source/drain region of a second active area are fashioned so as to intermingle with and be a part of the conductive layer opposing ends. Mutuality of dopants within the source/drain regions interconnected by the conductive layer causes formation of an electrically conductive path across the conductive layer, underneath the isolation dielectric.
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Dawson Robert
Fulford Jr. H. Jim
Advanced Micro Devices , Inc.
Daffer Kevin L.
Fourson George
Kowert Robert C.
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