Substrate with enhanced properties for planarization

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Reexamination Certificate

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C257S783000, C257S797000, C257SE21243, C257SE21249

Reexamination Certificate

active

10979849

ABSTRACT:
A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.

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Wolf, et al., “Silicon Processing for the VLSI Era, vol. 1: Process Technology,”60 Lattice Press, 1986, pp. 238-239.
Wolf et al., “Silicon Processing for the VLSI Era,” vol. 1: Process Technology, Lattice Press, 1986, pp. 238-239.

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