Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-03-16
2001-11-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06316985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a substrate voltage generating circuit and a semiconductor integrated circuit device, and particularly relates to a substrate voltage generating circuit, which uses transistor having thin gate oxide films, as well as a semiconductor integrated circuit device.
2. Description of the Background Art
Present dynamic random access memories, which will be referred to as “DRAMs” hereinafter, use constant power supply voltages. However, the DRAM is internally provided with a substrate voltage generating circuit, which is arranged on a chip and generates a negative voltage for the purposes of (1) preventing a pn junction in the chip from being forwardly biased in a minimum manner, (2) reducing a change in threshold voltage of a MOS transistor due to a substrate effect, (3) increasing a threshold voltage of a parasitic MOS, (4) reversely biasing and thereby reducing a junction capacity, and others.
A structure of a substrate voltage generating circuit
700
in the prior art will be described below with reference to FIG.
16
. Referring to
FIG. 16
, a substrate voltage generating circuit
700
includes a ring oscillator
702
and a charge pump
704
.
Ring oscillator
702
includes inverters
71
,
72
and
73
. Charge pump circuit
704
includes a capacity element C
70
and a PMOS transistor Q
70
. Capacity element C
70
receives a clock signal issued from oscillator
702
. PMOS transistor Q
70
is connected between capacity element C
70
and a substrate voltage output node OUT. A charge pump operation is repeated based on the output of oscillator
702
so that electrons (VBB) are supplied to a substrate (not shown).
In recent years, the power supply voltages have been increasingly lowered. This is because lowering of the operation voltages is unavoidably required due to lowering of transistor breakdown voltages, which is caused by miniaturization of transistors. Accordingly, it is demanded to provide a charge pump circuit of a boost type, which uses a low power supply voltage and has high pump efficiency.
In particular, a large substrate current occurs during accessing of a device so that such a circuit is required that supplies a large current commensurate with it and provides a predetermined negative voltage (substrate voltage) VBB.
Meanwhile, a gate oxide film thickness tox of transistors has been reduced in accordance with scaling of devices. If a charge pump circuit of a boost type is used, an intensity of an electric field applied to a channel of a transistor increases. This results in extreme increase in energy of carriers moving through the channel, and therefore extremely increases a possibility of generation of hot carriers. Hot carriers thus generated cause shifting of a threshold voltage and lowering of a mutual conductance, and therefore causes a problem that device characteristics are deteriorated over time. This impairs the reliability.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a substrate voltage generating circuit, which has high pump efficiency ensuring reliability even if transistors having thin gate oxide films are used, as well as a semiconductor integrated circuit device including the same.
A substrate voltage generating circuit according to the invention includes a voltage output terminal issuing a substrate voltage; a voltage supply circuit for supplying a voltage to the voltage output terminal in response to a clock signal; a switch circuit arranged between the voltage supply circuit and the voltage output terminal; a drive circuit including a boost node and a first capacity element boosting a voltage on the boost node in response to the clock signal; and provided for turning on/off the switch circuit with the voltage on the boost node; and a clamp circuit for clamping the level of the voltage on the boost node to a constant level.
As a major advantage, the invention can provide the substrate voltage generating circuit of a boost type, in which the boost level can be clamped to a predetermined value, and thereby a maximum electric field applied to a gate oxide film of a transistor can be suppressed. As a result, the circuit can generate a substrate voltage with high pump efficiency even when the power supply voltage is low, and can have high reliability.
In particular, an output transistor may be driven by pump operations in two stages. At this time, a capacity ratio between two capacity elements is controlled. Thereby, the boost level can be suppressed.
According to another aspect, a substrate voltage generating circuit includes a voltage output terminal issuing a substrate voltage; a voltage supply circuit for supplying a voltage to the voltage output terminal in response to a clock signal having an amplitude corresponding to a power supply voltage; a switch circuit arranged between the voltage supply circuit and the voltage output terminal; a drive circuit including a changing circuit for changing the clock signal having the amplitude corresponding to the power supply voltage into a clock signal having an amplitude corresponding to a boosted power supply voltage produced by boosting the power supply voltage, and a capacity element receiving the clock signal having the amplitude corresponding to said boosted power supply voltage, and provided for turning on/off said switch circuit based on a pump operation of said capacity element.
According to another advantage of the invention, the clock signal having an amplitude of the boosted power supply voltage level may be applied to the capacity element, whereby the charge pump operation can be performed without an influence by a change in an external power supply voltage.
In particular, the boosted power supply voltage level may be smaller than double the power supply voltage level. Thereby, it is possible to suppress the maximum electric field applied to the gate oxide film of the transistor. As a result, the circuit can generate the substrate voltage with high pump efficiency even when the power supply voltage is low, and can have high reliability.
According to still another aspect of the invention, a semiconductor integrated circuit device includes a clock generating circuit for generating a clock signal, a voltage output terminal issuing a substrate voltage; a voltage supply circuit for supplying a voltage to the voltage output terminal in response to the clock signal; a switch circuit arranged between the voltage supply circuit and the voltage output terminal; a drive circuit including a boost node and a first capacity element boosting a voltage on the boost node in response to the clock signal; and provided for turning on/off the switch circuit with the voltage on the boost node; and a clamp circuit for clamping the level of the voltage on the boost node to a constant level.
As another advantage of the invention, the boost level can be clamped to a predetermined value in a substrate voltage generating circuit of a boost type, and thereby a maximum electric field applied to a gate oxide film of a transistor in a charge pump can be suppressed. As a result, the circuit can generate a substrate voltage with high pump efficiency even when the power supply voltage is low, and can have high reliability.
In particular, an output transistor may be driven by pump operations in two stages. At this time, a capacity ratio between two capacity elements is controlled. Thereby, the boost level can be suppressed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4628214 (1986-12-01), Leuschner
patent: 5023465 (1991-06-01), Douglas et al.
patent: 5357416 (1994-10-01), Kitano et al.
patent: 5673232 (1997-09-01), Furutani
patent: 5831470 (1998-11-01), Park et al.
patent: 5909141 (1999-06-01), Tomishima
patent: 08-149801 (1996-06-01), None
An Efficient Back-Bias Generator with Hybrid Pumping Circuit f
Kobayashi Mako
Yamazaki Akira
Cunningham Terry D.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tra Quan
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