Substrate structure for composite semiconductor device

Details Substrate structure for composite semiconductor device Substrate structure for composite semiconductor device

1989-01-03

1991-01-15

James, Andrew J.

Fishing, trapping, and vermin destroying

357 48, 357 55, 437 62, H01L 2120, H01L 2176, H01L 2138

Patent

active

049857452

ABSTRACT:
The main surface of a first semiconductor substrate is bonded to the main surface of a second semiconductor substrate with an insulation film interposed therebetween to form a composite substrate. The first semiconductor substrate and insulation film are selectively etched to form an etched portion which reaches at least the second semiconductor substrate. An impurity layer with an impurity concentration different from that of the first semiconductor substrate is formed on or in the surface area exposed to the etched portion of the first and second semiconductor substrates. An epitaxial layer having an impurity concentration different from that of the impurity layer is formed in the etched portion. The first semiconductor substrate, impurity layer and epitaxial layer are planarized. The first semiconductor substrate, impurity layer and epitaxial layer are etched to make a pattern of the impurity layer on the surface of the composite substrate and the composite semiconductor substrate is aligned for formation of elements based on the pattern. The elements are formed in the composite substrate thus aligned.

REFERENCES:
patent: 4261003 (1981-04-01), Magdo et al.
patent: 4283235 (1981-08-01), Raffel et al.
patent: 4408386 (1983-10-01), Takayashiki et al.
patent: 4494303 (1985-01-01), Celler et al.
patent: 4501060 (1985-02-01), Frye et al.
patent: 4523370 (1985-06-01), Sullivan et al.
patent: 4601779 (1986-07-01), Abernathey et al.
patent: 4624047 (1986-11-01), Tani
patent: 4638552 (1987-01-01), Shinbo et al.
patent: 4661832 (1987-04-01), Lechaton et al.
patent: 4710794 (1987-12-01), Koshino et al.
patent: 4784970 (1988-11-01), Solomon
Lambotkar, "High performance transistor structure," IBM TDB, vol. 27, No. 7B, Dec./84, pp. 4517-4520.
K. G. Ashar, "Insulating layer pedestal transistor," IBM TDB, vol. 14, No. 5, Oct. 71, p. 1595.
Spencer et al., "Gas mixture control permits nonselective reactive ion etching," vol. 21, No. 4, 9/78, pp. 1518-1519.
Kemlage et al., "Dielectric Isolation," IBM TDB, vol. 16, No. 9, Feb./74, pp. 2869-2870.
U.S. Pat. Appln. Ser. No. 06/911,895 filed Sep. 26, 1986.
U.S. Pat. Appln. Ser. No. 07/215,381 filed Jul. 5, 1988.
Ohata et al., "Dielectrically Isolated Intelligent Power Switch," IEEE 1987 Custom Integrated Circuits Conference, Jul. 1987, pp. 443-446.

Affiliated with

Also associated with

Rating

Substrate structure for composite semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate structure for composite semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate structure for composite semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-58417