Substrate structure

Details Substrate structure Substrate structure

2000-05-12

2001-08-28

Gaffin, Jeffrey (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000

Reexamination Certificate

active

06281447

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming contact openings.
BACKGROUND OF THE INVENTION
One aspect of semiconductor processing involves making contact to or electrical connection with integrated circuitry devices, such as conductors or conductive lines which underlie one or more layers of material provided over a substrate. One prior art method of making such connection utilizes contact pads. These are enlarged conductive areas which are typically rectangular or square in shape and operably connected with the integrated circuitry device with which electrical connection is desired. The enlarged pad area provides a degree of tolerance for mask misalignment to still achieve the desired contact without causing an electrical short with other adjacent circuitry. The larger contact pad areas, however, consume valuable wafer surface area which could desirably be used for additional circuitry.
The problem is exemplified in
FIG. 1
, where a portion of an integrated circuit is indicated generally at
10
. Integrated circuit
10
Comprises a substrate
11
atop which a conductor
12
is formed. An insulative layer
13
is provided over conductor
12
and corresponding substrate surface area adjacent the conductor. A contact opening
14
of a minimum desired dimension is formed through a photoresist layer
19
, but because it is slightly misaligned to the left, a corresponding portion of insulative layer
13
directly overlying substrate
11
is undesirably removed. Such can also result in etching into substrate
11
, as shown.
One prior art proposed solution is set forth in
FIGS. 2 and 3
. There, a portion of integrated circuitry
10
a includes an insulative or semiconductive substrate
11
having an enlarged contact pad
15
formed thereon. A conductive line
16
is formed over substrate
11
and a connects with contact pad
15
. The goal is ultimately to make electrical connection with line
16
.
An insulative layer
17
is formed over contact pad
15
. A contact opening
18
is targeted to be etched to contact pad
15
. As shown, contact pad
15
is made considerably larger than the resultant contact opening
18
to provide a tolerance for contact mask misalignment. As an example, two representative contact mask misalignments are shown (FIG.
2
). A first contact mask misalignment is shown in dashed lines at
20
and represents a lateral and rotational displacement of the contact opening from the desired central location shown in solid lines. A second contact mask misalignment is shown in dash-dot lines at
22
and represents a simple misplacement in the negative x-direction. Either way, the contact opening falls within the boundary of the contact pad and the desired electrical connection is made. Accordingly, the wider-dimensioned contact pad tolerates mask misalignments, but at the expense of consuming precious wafer real estate.
This invention grew out of concerns associated with conserving wafer space or area. This invention also grew out of concerns associated with reducing or decreasing the area required, for a contact pad.
SUMMARY OF THE INVENTION
Semiconductor methods of forming self-aligned contact openings are described. In a preferred implementation, a conductor is formed over a substrate. A first layer of material is formed over the conductor. A second layer of material is formed over the first layer of material. The first and second layer materials can be etchably different. Portions of the first and second layers are then removed to form a contact opening to the conductor. According to one aspect, the second layer material is removed at a slower rate than the rate at which first layer material is removed. According to another aspect, portions of such layers are removed at the same time. According to still another aspect of the invention, the second layer material comprises a sacrificial spun-on material.


REFERENCES:
patent: 5198386 (1993-03-01), Gonzalez
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 5598027 (1997-01-01), Matsuura
patent: 5619072 (1997-04-01), Mehta
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5872056 (1999-02-01), Manning
patent: 5982035 (1999-11-01), Tran et al.

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