Substrate strips for use in integrated circuit packaging

Details Substrate strips for use in integrated circuit packaging Substrate strips for use in integrated circuit packaging

1999-10-14

2001-08-21

Nguyen, Tuan H. (Department: 2813)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C438S017000, C438S111000, C361S823000, C029S847000

Reexamination Certificate

active

06278618

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to packaging for integrated circuit devices. More particularly, it relates to forming substrates that facilitate testing integrated circuits mounted thereon in strip or panel form.
In the semiconductor industry, there are ongoing efforts to provide smaller, less expensive and faster integrated circuit devices. One aspect of these efforts is directed at the development of more efficient packaging structures, arrangements and processes. One common packaging arrangement is known as grid array based packaging (e.g., ball grid arrays, pin grid arrays, etc.). In a grid array type package, a die is typically mounted on the top surface of a substrate that has an array of contacts on its bottom surface. The die is then electrically connected to landings on the top surface of the substrate. The substrate provides electrical routing and connectivity between the landings on the top surface of the substrate and the contacts on the bottom surface.
Typically, during packaging, substrate strips or panels are provided that have a plurality of distinct molding areas. For lack of the availability of a common term, the molding areas are referred to as tiles herein. The tiles are typically (although not always) separated by thermal expansion slots. A representative substrate strip
101
is illustrated in FIG.
1
. Traditionally, a single die was mounted in a die attach area
103
near the center of each tile
102
. The die is then electrically coupled to landings
105
on the top surface of the tile
102
. The die may be electrically coupled to the landings by a variety of traditional techniques, although wire bonding is most common. The landings
105
are coupled to associated vias
107
by traces
109
on the top surface of tile
102
. The vias
107
are electrically conductive and pass through substrate. The vias are then typically coupled to associated contacts (not shown) on the bottom surface of the substrate by traces (not shown) on the bottom surface of the substrate.
After the dice on a particular strip have all been mounted and electrically connected, a plastic cap is typically formed over each die. The packaged integrated circuits are then typically trimmed (i.e. the excess portions of the strip are trimmed away thereby separating the packed integrated circuits from one another). Thereafter, the packaged integrated circuits are typically tested.
As die and package sizes have been reduced, there have been recent efforts to mount a plurality of dice within each tile (molding area) with the intention and result of forming several distinct integrated circuit packages on each substrate tile. Although this approach has many advantages, due to the nature of the way that the substrate strips are formed, the packages cannot be tested in the strip form. Rather, the packaged devices are singulated and then tested in the singulated form.
Although the existing substrate arrangements and individual testing have worked well in the past, as smaller and higher density packaging becomes more common, improved substrate strip structures and improved testing techniques that are less expensive and have less problems than the current structures and techniques will become necessary and desirable.
SUMMARY OF THE INVENTION
To achieve the forgoing and other objects and in accordance with the purpose of the invention, a variety of improved substrate structures and substrate fabrication techniques are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. In one aspect a substrate strip having a plurality of vias and metalization that defines a plurality of landings located on a top surface and a plurality of contact pads on a bottom surface is formed. The patterning also defines buss lines and/or interconnection features which electrically couple various landings. Portions of the landings (which by way of example may be formed from copper) are plated with one or more further metallic layers (such as gold or gold in combination with a barrier layer). The landings are electrically charged or grounded during at least a portion of the plating of these further metallic layers to facilitate the plating (as for example is required in electrolytic plating). The electrical connections between a most of the bond fingers are severed after the further metallic layer plating by removing at least a portion of the buss lines and/or interconnection features, without separating the substrate segments. In a preferred embodiment, the electrical connections between the bond fingers are provided to facilitate the plating of the further metallic layers. The connections are severed to permit strip testing of dice that are eventually mounted on the substrate. In some embodiments, some of the electrical connections are retained to permit non-stick detection during wire bonding.
In another aspect of the invention, a method of packaging integrated circuits is described that is suitable for facilitating strip testing of a large number of integrated circuits that are mounted on the strip. In this aspect a plurality of dice are mounted on a substrate strip that has a plurality of molding areas. Each molding area includes an array of substrate segments (e.g. a two dimensional array of substrate segments). Each substrate segment has a die attach area and a plurality of landings located on a top surface and a plurality of contact pads on a bottom surface. The dice are electrically connected to the substrate by a suitable technique such as wire bonding. The dice are then encapsulated and electrically tested in strip format. In some embodiments, non-stick detection wiring bonding is used.
In yet another (quite distinct) aspect of the invention, a substrate strip for use in integrated circuit packaging is described. The substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias. The landings have bond pads suitable for use in wire bonding and are preferably arranged in at least one row that extends adjacent or around the die attach area. The contact pads are positioned opposite the landings. With this arrangement, extended routing traces are not required to electrically couple the bond pads to the contact pads.
In some embodiments, the landings/contacts are arranged in one or more rows about the die attach area. multiple rows of landings/contacts are provided. When desired, the substrate strips can be fabricated in panels that have a plurality of the described strips.


REFERENCES:
patent: Re. 36773 (2000-07-01), Nomi et al.
patent: 5990547 (1999-11-01), Sharma et al.
patent: 6043559 (2000-03-01), Banerjee et al.

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