Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2011-05-31
2011-05-31
Loke, Steven (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S776000
Reexamination Certificate
active
07952168
ABSTRACT:
A substrate strip for semiconductor packages to slow the crack growth, primarily comprises a molding area and two side rails. The molding area includes a plurality of packaging units. The side rails are located outside the molding area and include two opposing longer sides of the substrate strip. A metal mesh is disposed on the side rails. The metal mesh consists of a plurality of crisscrossed wires having a plurality of isolated wire terminals at one edge of the metal mesh. Accordingly, crack growth is slowed by the specific metal mesh without damaging the packaging units. In one embodiment, the metal mesh is without boundary wires connecting to the isolated wire terminals to enhance the resistance to crack growth.
REFERENCES:
patent: 5519176 (1996-05-01), Goodman et al.
patent: 5923539 (1999-07-01), Matsui et al.
patent: 7091583 (2006-08-01), Chen et al.
patent: 7217993 (2007-05-01), Nishimura
Loke Steven
Muncy Geissler Olds & Lowe, PLLC
Powertech Technology Inc.
Thomas Kimberly M
LandOfFree
Substrate strip for semiconductor packages does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Substrate strip for semiconductor packages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate strip for semiconductor packages will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2673635