Substrate pumped ESD network with trench structure

Details Substrate pumped ESD network with trench structure Substrate pumped ESD network with trench structure

1999-03-01

2002-06-25

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06411480

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electrostatic discharge protection devices for the input/output circuits of an integrated circuit. Specifically, an NMOS device is provided having a lower trigger threshold for discharging any electrostatic voltages which appear on a terminal of the integrated circuit.
The manufacture of integrated circuits for CMOS or NMOS implemented devices often include an electrostatic discharge device( ESD) connected to each of the input or output pins of the integrated circuit. In the event that an electrostatic charge is coupled to an input or output pin of the device, an ESD protection device will drain the charge safely away from the functional circuit connected to a respective terminal. These ESD devices are located on all pins which connect to functional circuitry which can be damaged by an electrostatic charge. The objective of the devices which utilize a MOSFET or CMOS FET, connected across the input pin, is to trigger the device in a snapback mode to conduct current at a lower threshold voltage than the connected functional circuitry, thereby shunting to ground the electrostatic charge to avoid damaging the functional circuitry.
The ESD devices are more difficult to implement in advanced integrated circuit technology. For instance, when thin epitaxial substrates are utilized, the substrate resistance is reduced and the conduction threshold of the MOS devices which make up the functional circuitry increases since more avalanche generation is needed at the drain substrate junction before the substrate/source junction forward biases. The increase in the threshold voltage for turning on the MOS device, when used in the ESD snap-back mode, renders it problematical that the device can be switched on before the functional circuitry is damaged by the incident electrostatic charge.
The ESD devices tend to be implemented as single finger or multiple finger devices for multiple terminals of the integrated circuit. When the ESD protection device is triggered OFF, the sustaining/holding voltage maintains the device on until the electrostatic charge has been safely shunted around the functional circuitry. As the threshold, or snap-back voltage increases, the voltage difference between the trigger/snap-back voltage and the sustaining holding voltage for maintaining the ESD protection device conductive increases. The result may be that only one of the multiple fingers is able to turn on, if the difference between the trigger and holding voltage is large. On the other hand, if the difference between the trigger and holding voltage for the ESD protection device is small, then when one of the ESD protection devices turns on, it will build up enough voltage to turn on the rest of the fingers and thus the entire parallel array of ESD protection devices are used to efficiently dissipate the electrostatic charge. The present invention is directed to an ESD protection device having a decreased trigger voltage and a lower voltage difference between the trigger and holding voltage for the device.
SUMMARY OF THE INVENTION
The present invention provides for a circuit which protects an integrated circuit from an externally applied transient voltage. The ESD protection device comprises a transistor placed in an isolated area of the integrated circuit substrate. The transistor operates in response to a positive potential electrostatic pulse either as a transistor in an “on” state, or in a snapback mode as a parasitic bipolar transistor which dissipates the electrostatic voltage connected to the integrated circuit terminal.
The transistor in a preferred embodiment is a MOS device which is maintained isolated by a trench guard ring on four sides of the MOS device, permitting charge pumping of the isolated substrate. During an ESD event, an electric charge is coupled to the isolated substrate area which pumps the isolated substrate area, increasing its voltage potential with respect to the remaining substrate area. The increased substrate potential requires less avalanche at the drain/substrate junction of the transistor. The result is a reduced threshold voltage to turn on the transistor, and a reduced snapback voltage necessary to turn on the parasitic bipolar transistor.
In one embodiment of the invention, a trigger circuit is used to charge the isolated substrate area by injecting carriers into the isolated substrate area in response to the electrostatic potential applied to the terminal.
In one embodiment of the invention, the trigger circuit may be a vertical bipolar transistor formed in the isolated substrate area. The vertical transistor has a collector, connected to charge the isolated substrate area, and an emitter tied to the input terminal so that current is applied to the isolated area of the substrate.


REFERENCES:
patent: 4400711 (1983-08-01), Avery
patent: 5301084 (1994-04-01), Miller
patent: 5400202 (1995-03-01), Metz et al.
patent: 5528188 (1996-06-01), Au et al.
patent: 5581103 (1996-12-01), Mizukami
patent: 5672527 (1997-09-01), Lee
patent: 5686751 (1997-11-01), Wu
patent: 5705841 (1998-01-01), Yu
patent: 5742085 (1998-04-01), Yu
patent: 5751042 (1998-05-01), Yu
patent: 5754380 (1998-05-01), Ker et al.
patent: 0 549 320 (1993-06-01), None
patent: 02-119262 (1990-05-01), None

Affiliated with

Also associated with

Rating

Substrate pumped ESD network with trench structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate pumped ESD network with trench structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate pumped ESD network with trench structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2983393