Substrate potential generating circuit generating substrate pote

Details Substrate potential generating circuit generating substrate pote Substrate potential generating circuit generating substrate pote

1993-10-22

1995-04-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327534, 327537, H03K 301

Patent

active

054081408

ABSTRACT:
A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.

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"A 80ns 5V-Dynamic RAM", by James M. Lee et al, 1979 IEEE International Solid-State Circuits Conference, pp. 142-143.

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