Substrate polishing device and method

Abrading – Flexible-member tool – per se

Reexamination Certificate

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C428S215000

Reexamination Certificate

active

06688956

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general to polishing pads used for creating a smooth, ultra-flat surface on such items as glass, semiconductors, dielectric/metal composites, magnetic mass storage media and integrated circuits. More specifically, the present invention relates to polishing pads made of extruded thermoplastic polymer compositions.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (CMP) is used increasingly as a planarizing technique in the manufacture of VLSI integrated circuits (ICs). It has potential for planarizing a variety of materials in IC processing but is used most widely for planarizing metallization layers and interlevel dielectrics on semiconductor wafers, and for planarizing substrates for shallow trench isolation.
The success of CMP over other methods of planarization derives from the ever-increasing needs for miniaturization in electronic devices, which requires tighter wafer planarity tolerances. Competing techniques, such as etchback, do not provide the required degree of wafer planarity that is achievable with the CMP technique. In CMP, a semiconductor wafer is polished using a repetitive, regular motion of a mechanical polishing wheel and a slurry, which may contain a mixture of fine particles and chemical etchants. By placing the slurry between the polishing wheel and the wafer, unwanted material may be successfully removed with a high degree of planarity. To aid in the planarization process, the polishing wheel commonly employs a specialized polishing pad that may be made from felted or woven natural fibers such as wool, urethane-impregnated felted polyester or various types of polyurethane plastic.
There are three critical consumable components in the CMP process. One is the abrasive liquid slurry. The abrasive liquid slurry's composition must be altered, and special formulations must be produced for each different substrate being polished. Some substrates require a high pH to be activated for polishing, and other substrates need a more acid environment. Still other substrates respond best to silica abrasives, while others require alumina or titanium abrasive particles. The second critical consumable component in the CMP process is the polishing pad. It must be very flat, uniform across its entire surface, and resistant to the chemical nature of the slurry and have the right combination of stiffness and compressibility to minimize effects like dishing and erosion. A third critical consumable component in the CMP process is the carrier film. The carrier film attaches the wafer to its rotating holder and must have an adequately flat and uniform in its thickness, must have an adhesive that will hold it tightly to the carrier but not too tightly to the wafer, all while being immune to the chemical environment in which it works.
Current polishing pads often prove inadequate due to increasing circuit integration density. During metal CMP, areas dense in features (i.e., alignment marks) tend to oxidize at a faster rate than areas with sparse distributions. This uncontrollable oxidation of the metals and the resultant aggressive mechanical loss are commonly referred to as erosion. Additionally, manufacturers have observed that oxide erosion in dense arrays increases dramatically as batch sizes are increased. It is also believed that current polishing pads contribute to “dishing” through deformation of the pad during polishing so that the center portion of larger circuit features are polished to a level lower than the exterior of the feature. Both effects contribute to lower surface planarity.
Another problem with current technology results from the process by which polishing pads are fabricated, rather than the properties inherent in the pad composition. One currently preferred method of pad fabrication is to pour a monomer of a thermosetting plastic, such as urethane, into a cylindrical mold. The monomer is then subjected to a thermal polymerization process. However, the polymerization occurs to varying degrees within the cylindrical mold, presumably due to heat transfer effects. The polymer material located near the center of the mold has different properties from that near the edges. Thus, a great variation in properties exists between pads cut from cross-sections near the top and bottom of the mold and those cut from the center. Likewise, the characteristics of an individual polishing pad made by this “sawed-log” technique may vary significantly from the outer regions of the pad to the center.
In another method, CMP pads are formed individually from a thermoplastic polymer by injection the thermoplastic material into a mold. While having the advantage of potentially reducing the variation in properties from pad to pad, this method causes undesirable intra-pad variations. Specifically, when the molten or uncured polymer is injected into the individual pad mold, a small amount of excess material is inevitably and undesirably formed on the surface of the polymer near the injection port. Such a phenomenon is known in the art as a “gate vestige” or “gating” of the pad. The undesirable effects of gating may be observed both locally, near the gate vestige itself, as well as throughout an individual pad.
Such manufacturing problems lead to less efficient polishing processes. Typically, these problems with conventional CMP polishing pads result in polishing processes may operate at only 60% uptime. Thus, it would be very beneficial if the process uptime could be increased.
Accordingly, what is needed in the art is an engineering design for a semiconductor wafer polishing pad that may be formed by a process that reduces intra- and inter-pad variation, while yielding polishing pads that are resistant to chemical degradation and provide a more uniform polishing by reducing erosion and dishing.
SUMMARY OF THE INVENTION
To address the deficiencies of the prior art, the present invention provides a polishing pad comprising an extruded thermoplastic polymer that is free of a gate vestige and a method of manufacturing therefor. In one embodiment, the present invention provides a extruded amorphous thermoplastic polishing pad that is free of a gate vestige.
In one exemplary embodiment, the present invention provides an extruded thermoplastic polishing pad wherein the thickness of the pad varies by less than 1%. In another embodiment, the pad has an elongation-to-break in the range of 25%-1000%. In certain embodiments the thermoplastic of the polish pad will have a critical surface tension greater than about 30 milliNewtons/meter.
In another aspect of the invention there is provided a method of manufacturing a polishing pad that includes extruding a thermoplastic material from an extrusion apparatus to produce an extruded thermoplastic material and forming a polishing pad that is free from a gate vestige and suitable for polishing a semiconductor wafer or integrated circuit from the extruded material. In certain embodiments, the method provides a polishing pad having a thickness that varies by less than 1%.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


REFERENCES:
patent: 4613345 (1986-09-01), Thicke et al.
patent: 5242742 (1993-09-01), Funk et al.
patent: 5605760 (1997-02-01), Roberts
patent: 6017265 (2000-01-01), Cook et al.
patent: 6063306 (2000-05-01), Kaufman et al.
patent: 6106754 (2000-08-01), Cook et al.
patent: 6126532 (2000-10-01), Sevilla et al.

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