Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-17
2003-03-04
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S697000
Reexamination Certificate
active
06528389
ABSTRACT:
BACKGROUND
The present invention generally relates to a method of fabrication of semiconductor devices. More specifically the present invention is directed towards the formation of planarized, dielectrically filled trenches and active areas on a semiconductor wafer substrate.
Increased miniaturization of integrated circuit devices requires a large number of surface conductors for the conveyance of digital signals from device to device. These devices differ in size and connectivity requirements. They include, but are not limited to transistors, diodes, capacitors and resistors. Some devices may have submicron feature sizes, while other devices on the same substrate may have much greater feature sizes. In addition to the miniaturization of active devices, active areas, contacts and electrically isolated areas, there also continues to be an increasing need for more interconnect layers which are themselves comprised of conductors having smaller dimensions. In order to accommodate the multiplicity of circuit devices an insulation means is required between them. Shallow trenches of varying widths are often used to isolate the various circuit devices.
Typically, shallow trenches are filled with a dielectric material such as silicon dioxide (SiO
2
) to aid in insulation. Assuring an even topology and uniform fill of the silicon dioxide becomes increasingly difficult as shallow trenches of diverse sizes are used in conjunction with active areas of varying device densities.
The growing complexities of the topography of semiconductors, especially with the use of shallow trenches of varying width, create a problem with surface planarity. In order to promulgate this densification of devices, there has been increased reliance on planarized dielectrically filled trenches for proper insulation of active areas.
Many different techniques have attempted to create trenches having vertical walls that can be uniformly filled with dielectric material and maintain planarity with the active areas of a substrate. Some techniques use various “dummy structures” inserted into the field areas to provide improved planarity during chemical mechanical polishing (CMP).
A typical cross section of a prior art trench isolation structure is shown in FIG.
1
. An active region silicon nitride layer
1
is deposited on the silicon surface
2
(including a pad oxide
3
under the silicon nitride). The silicon nitride layer will act as a protective layer over each active area
9
and act as a stop layer for the CMP process. A trench
4
is etched into a silicon substrate wafer
8
using photolithography to form isolation trenches and deposited with an oxide such as silicon dioxide
5
afterwards. The SiO
2
deposition forms to the topology on the silicon surface and reflects the topology of the coated surface.
An example of the topology of the oxide is shown in
FIG. 1
at time=0. The chemical mechanical polishing process will first polish down the high features and erode the side walls,
FIG. 1
at time t1. The process will continue in a similar manner at time t2. As the polishing process continues, the high features will continue to erode until an equilibrium planarity is obtained as illustrated in time t3. Once the equilibrium planarity is obtained, the planarity will not improve with additional polishing, as illustrated in time t4. At t3 and t4, the topology in the trench areas continues to include low features and does not show perfect planarity. When the polish process contacts the silicon nitride layer, the polish rate of the silicon nitride will be significantly lower than the oxide material. This selectivity causes more oxide to be removed in trench areas, and thus, recess the oxide even further. As the polish process continues, the degree of planarity is further aggravated. Therefore, improvement is needed in creating uniform planarity across the semiconductor surface.
SUMMARY OF THE INVENTION
Accordingly, this invention provides an improved method of planarizing a semiconductor substrate for use with an integrated circuit and the planarized semiconductor substrate. To improve planarity, chemical mechanical polishing is controlled through the use of a first stop layer
1
patterned with an active mask to define active areas formed over the top of a silicon substrate
8
and a pad oxide layer
3
. A second stop layer
6
or
11
is formed over a dielectric filler layer
5
, said filler layer
5
being formed over the first stop layer. A sequence relating to the application of a second stop layer and chemical mechanical polishing can be varied to accommodate specific circumstances.
In one embodiment equilibrium planarity is obtained from chemical mechanical polishing,
FIG. 1
, time=t3 of a dielectric oxide filler material
5
such as silicon dioxide. The filler material being applied after etching of the first stop layer. A second stop layer
6
comprising a material harder than the dielectric oxide filler material
5
is deposited on the polished surface of the filler material. For example the second stop layer may comprise polysilicon or silicon nitride. In this embodiment the second stop layer can be patterned in a uniform design across the entire surface, or patterned such that it will generally cover the shallow trench areas using a reverse mask of an active mask used in forming active areas.
The stop layer
6
can be applied in a pattern such as a “checkerboard” pattern (
FIG. 10
) whereby the density of the pattern is used to further control the rate of material removal during CMP. In the alternative the stop layer
6
can be generally formed on the filler layer over the valley regions of the trench areas
4
(
FIG. 2
) using a reverse active mask.
The reverse active mask stop layer slows the removal rate of silicon dioxide filler over the trench area during CMP and effectively increases material removal over the active area. As the silicon dioxide thickness is decreased in the active area during CMP, a valley
7
will form over the active area. During this same period of time, the CMP will slowly be removing the stop layer from over the trench areas. The stop layer will eventually be removed completely by CMP; however, a valley
7
over the active area should occur first. When the stop layer has been removed over the trench area
4
, and a valley
7
has been formed over the active areas,
FIG. 3
, the removal rates over the active and trench areas will be equal until the polish reaches the first stop layer over the active areas. The removal rate of the continuing CMP will be slowed by the first stop layer masked over the active areas. This slowing allows the oxide in the trench areas to become planar with the first stop layer over the active areas, thereby improving the degree of planarity across the semiconductor device surface. (FIG.
4
).
In another embodiment a second stop layer
11
is formed over a filler layer that has not been subjected to CMP. (
FIG. 5.
) The second stop layer is etched with a reverse tone pattern that opens the areas above the active areas
9
. (
FIG. 7.
) CMP is then performed to planarize the surface. The opened areas are reduced more quickly than the areas covered by the second stop layer and planarization is thereby improved. The reverse tone etch can be used to etch through the second stop layer
11
into the filler layer
5
,
FIG. 7
or through the second stop layer
11
and the filler layer
5
to reach the first stop layer
1
, FIG.
8
. In addition a reverse tone mask can allow for overlap
10
of the active areas by the second stop layer.
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pa
Allman Derryl D. J.
Gregory John W.
Brock II Paul E
Hitt Gaines & Boisbrun P.C.
Lee Eddie
LSI Logic Corporation
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