Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1998-04-01
1999-06-22
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
216 11, 216 14, 216 52, 438694, H01L 2100, B44C 122
Patent
active
059142740
ABSTRACT:
A bi-layer bump comprises a base layer composed of sprayed aluminum thick film having a thickness of about 20 .mu.m formed to cover the periphery of the passivation film formed on each pad electrode, a surface layer composed of sprayed copper thick film having a thickness of about 30 .mu.m formed on the base layer. According to the above-mentioned structure, a substrate on which bumps are formed which has an excellent electric property and connecting reliability, wherein an interlayer insulating layer, an active layer and a multi-layer wiring can be provided under the pad electrode can be obtained.
REFERENCES:
patent: 4887760 (1989-12-01), Yoshino et al.
patent: 5246880 (1993-09-01), Reele et al.
patent: 5336547 (1994-08-01), Kawakita et al.
patent: 5487999 (1996-01-01), Farnworth
"High Reliability Chip-Joining Process", IBM Technical Disclosure Bulletin, vol. 33, No. 12, pp. 237-238.
Asabe Mitsuo
Mitani Tsutomu
Yamaguchi Kazufumi
Matsushita Electric - Industrial Co., Ltd.
Powell William
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