Substrate mapping

Details Substrate mapping Substrate mapping

2003-04-25

2004-10-26

Pert, Evan (Department: 2827)

Semiconductor device manufacturing: process

With measuring or testing

Optical characteristic sensed

Reexamination Certificate

active

06808947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to mapping techniques for semiconductor substrates. More specifically, the present invention relates to methods and apparatus for identifying defective die sites and good die sites on semiconductor mounting substrates of any type and, if necessary, attaching defective dice to the defective die sites and, if necessary, attaching good dice to the good die sites.
2. State of the Art
In the fabrication of semiconductor packages, semiconductor dice (also known as “semiconductor devices” or “semiconductor chips”) are typically mounted and electrically connected to carrier substrates appropriate for the chip type and the subsequent use of the package. For example, chip-on-board (COB), board-on-chip (BOC), ball grid array (BGA), chip-scale, or leads-over-chip (LOC) mounting arrangements may be made on printed circuit boards strips, tape frames and other carrier substrates known in the art. After die attach (the mounting of the semiconductor die to the carrier substrate), the hybrid combination of components is electrically connected, generally through wire bonding, conductive adhesives or solder reflow and encapsulated for protection. The finished package is then made available for use in a wide variety of applications.
Semiconductor dice and carrier substrates are distinct components which are manufactured by separate processes. Individual integrated circuit dice are usually formed from a larger structure known as a semiconductor wafer, which is typically comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide are also sometimes used. Each semiconductor wafer has a plurality of integrated circuit semiconductor dice and/or circuitry, arranged in rows and columns with the periphery of each integrated circuit being substantially rectangular in shape, the integrated circuits of the semiconductor dice being formed through a combination of deposition, etching, and photolithographic techniques. The inactive silicon backsides of the wafers are typically thinned (i.e., have their cross sections reduced) by a mechanical and/or chemical grinding process, and the wafers sawed or “diced” into substantially rectangularly shaped discrete integrated circuit semiconductor dice. The nature and complexity of the process for fabricating integrated circuits make the manufacturing cost of an individual semiconductor die relatively high.
With respect to the various carrier substrates for COB, BOC, BGA, LOC, chip-scale, and other types of packages, each of the carrier substrates is generally manufactured with several common features: an attachment site for at least one semiconductor die, a plurality of bond pads and conductive traces for interconnecting conductors on one or more semiconductor dice, a resist or insulating layer for electrically isolating the conductive traces and interconnections, tooling holes on the substrate edges for automated machine handling, and alignment marks for semiconductor die placement, wire bonding, and substrate orientation. The electronic properties and performance of the carrier substrate are determined by precise characteristics of the conductive layers and insulation layers which form it, including the composition, thickness, and surface quality of the various types of layers.
Currently, many carrier substrates (also referred to as “mounting substrates”) have multiple die attach sites per carrier substrate, which may further be formed in an array arrangement of several across or a matrix of columns and rows. Such high-density arrays or matrices are suitable for increased throughput in automated processing, such as die attach processing, as well as desirable for use in various electronics applications. The array or matrix of die attach sites of any given substrate may range, for example, from a 2×3 matrix (2 columns×3 rows) to a 20×20 matrix. Typically, a 2×3 matrix for a BGA-type carrier substrate
10
is depicted in drawing FIG.
1
. Semiconductor die sites
20
, for mounting and electrical attachment of a semiconductor die to each site
20
, are configured in an arrangement of two columns and three rows. Pin one indicators
22
and fiducial marks
24
, which provide orientation for vision systems associated with automated machine handling and semiconductor die placement apparatus (not shown), are formed as openings in a layer of solder resist
26
on carrier substrate
10
. Semiconductor die sites
20
are shown with solder balls
32
of the BGA surrounding each semiconductor die receiving area
50
and configured in a ball grid array arrangement
54
. The solder balls
32
are typically placed on contact pads (not shown), which are further electrically interconnected to circuit traces (not shown) underlying a passivation layer of solder resist
26
on the surface of the carrier substrate
10
. The circuit traces are, in turn, electrically connected to other contact pads within or immediately proximate to semiconductor die sites
20
.
After die attach, conductive wires extending from the active surface of the mounted semiconductor die are typically wire bonded onto the contact pads in the semiconductor die site
20
of the carrier substrate
10
. The conductive traces, contact pads, and other contact pads are typically formed by laminating or depositing a metal material (e.g., copper) onto a base insulating substrate material. Subsequent photolithographic and etching techniques are then used to define the actual conductive patterns.
Referring again to drawing
FIG. 1
, carrier substrate
10
also includes a layer of solder resist
26
. The layer of solder resist
26
is applied using photolithographic processes onto carrier substrate
10
and serves to mask or shield conductive members on the top and bottom carrier substrate surfaces during subsequent soldering and/or plating processes and/or various other processes. Various solder resist materials are well known and commercially available for such processes. With respect to the surface of carrier substrate
10
, solder resist layer
26
may mask all portions of the surface except the semiconductor die sites
20
and the contact pads for placement of solder balls
32
. As previously described, pin one indicator
22
and fiducial marks
24
are typically formed as openings in solder resist layer
26
subsequent to the deposition thereof. Any conductive elements within semiconductor die site
20
thus remain exposed, as does at least a portion of the contact pads, after application of solder resist layer
26
to the top surface of the carrier substrate
10
.
In the process of die attach, a die attach apparatus typically uses a vision system to locate a fiducial mark
24
, pin one indicator
22
, and/or any other alignment feature on the lead frame or other mounting substrate. Using an X-Y table for proper alignment, the vision system checks the semiconductor die position on the die pickup tool and directs the apparatus to adjust the substrate and die pickup tool into the correct positions for precise semiconductor die placement. Typically, semiconductor dice are presented to a die attach apparatus in sawed wafer form and are mounted on wafer tape for attachment on metal lead frames or any suitable substrate. For some die attach apparatus, semiconductor dice may also be presented in gel or waffle pack form for attachment to the desired substrate. In the die bonding process, semiconductor dice are selectively picked from those of wafers respectively probe-tested in their manufacturing factories using various testing equipment. To orient the semiconductor dice, the die bonder's vision system identifies a feature on a die and directs the X-Y table to pick up and align the die in the X, Y, and theta directions. Meanwhile, a mounting substrate has been indexed to the die attach site and properly oriented. At the die attach site, a precise amount of adhesive, such as epoxy resin, is applied. The picked-up die is then bonded to the die attach site of the mounting subst

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