Substrate isolation in integrated circuits

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S525000, C257SE21551

Reexamination Certificate

active

07358149

ABSTRACT:
Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

REFERENCES:
patent: 4580331 (1986-04-01), Soclof
patent: 4653177 (1987-03-01), Lebowitz et al.
patent: 5013673 (1991-05-01), Fuse
patent: 5448090 (1995-09-01), Geissler et al.
patent: 5960276 (1999-09-01), Liaw et al.
patent: 6066885 (2000-05-01), Fulford et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6537888 (2003-03-01), Lee
patent: 6787409 (2004-09-01), Ji et al.
patent: 2003/0170964 (2003-09-01), Kao et al.
patent: 2005/0012173 (2005-01-01), Sheu et al.
Jank, M.P.M.; Lemberger, M.; Ryssel, H. “Gate Oxide Damage Due To Through The Gate Implantation in MOS-Structures with Ultrathin and Standard Oxides” Ion Implantation Technology 2000 Conference; Meeting Date: Sep. 17-22, 2000; Alpbach, Austria, pp. 103-106.
Shibahara, K.; Fujimoto, Y.; Hamada M.; Iwao, S.; Tokashiki, K.; and Kunio, T. “Trench Isolation With (NABLA)—Shaped Buried Oxide for 256 Mega-Bit Drams” IEEE 1992, pp. 10.5.1-10.5.4.
Fuse, G.; Fukumoto, M.; Shinohara, A.; Odanaka, S.; Sasago, M.; Ohzone, T. “A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect” IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, pp. 356-360.
Ohe, K.; Odanaka, S.; Moriyama, K.; Hori, T.; Fuse, G. “Narrow-Width Effects of Shallow Trench-Isolated CMOS with n+−Polysilicon Gate” IEEE Transactions on Electron Devices, vol. 36, No. 6, Jun. 1989, pp. 1110-1116.
Stanly Wolf, “Silicon Processing For the VSLI Era” vol. 1 Lattice Press, 1986, pp. 208, 395.
Stanly Wolf, “Silicon Processing For the VSLI Era” vol. 2 Lattice Press, 1990, pp. 570,619,633.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Substrate isolation in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate isolation in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate isolation in integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2772138

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.