Substrate including barrier solder bumps to control...

Details Substrate including barrier solder bumps to control... Substrate including barrier solder bumps to control...

2007-06-21

2010-10-26

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000, C257SE21508

Reexamination Certificate

active

07821131

ABSTRACT:
A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry; and a plurality of solder bumps including: die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region.

REFERENCES:
patent: 6614122 (2003-09-01), Dory
patent: 2002/0121707 (2002-09-01), Pendse et al.
patent: 2002/0167075 (2002-11-01), Madrid
patent: 01290292 (1989-11-01), None
patent: 10189819 (1998-07-01), None

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