Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1986-12-09
1988-11-22
Morgenstern, Norman
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
4271263, 4271265, 174 685, 361402, 361411, 428601, B05D 512, H05K 109
Patent
active
047865237
ABSTRACT:
In a wired substrate, a conductive pattern is formed of an alloy of gold, a base metal, and a noble metal and is contiguous to an insulating layer of a mixture of oxides of the base and the noble metals. The alloy preferably includes the base and the noble metals to a total amount of 0.2 to 2 percent by weight. More preferably, the base metal is titanium, aluminum, or copper. The noble metal is palladium, ruthenium, rhodium, or nickel. The wired substrate is manfactured by forming a first layer of the base metal, a second layer of the noble metal, and a selectively formed gold layer successively on the substrate and by heat treating at least the first, the second, and the gold layers to convert the gold layer and those portions of the first and the second layers on which the gold layer is formed, to the conductive pattern and to concurrently convert other portions of the first and the second layers to the insulating layer. The first, the second, and the gold layers are preferably 0.025 to 0.4, 0.025 to 0.3, and 1 to 10 microns thick, respectively. When the base and the noble metals are titanium and palladium, respectively, the heat treatment is carried out in air at 850.degree. to 950.degree. for 5 to 10 minutes.
REFERENCES:
patent: 4153518 (1979-05-01), Holmes
patent: 4434544 (1984-03-01), Dohya
patent: 4525383 (1985-06-01), Saito
patent: 4628149 (1986-12-01), Dohya
Morgenstern Norman
Nippon Electric Co. Ltd.
Padgett Marianne L.
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