Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-12-21
2002-05-28
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S783000, C438S106000
Reexamination Certificate
active
06396135
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor packaging, and more specifically to mechanisms for improving environmental resistance of semiconductor packages.
BACKGROUND
In the development of new semiconductor packages, one constant concern is the package's overall environmental resistance. One important feature of environmental resistance is moisture sensitivity. The moisture sensitivity concerns are sufficiently large that standard ratings have been promulgated for measuring environmental resistance. For example, JEDEC has promulgated moisture sensitivity testing standards that generally identify four levels of moisture resistance for semiconductor packages (i.e., the JEDEC MSL rating in which level 4 is the lowest resistance and level 1 is the highest). In practice, it is often desirable for manufactures to identify the JEDEC MSL rating of a particular package. Customers (as well as the manufactures) often utilize this information in determining features such as permissible shelf life, acceptable applications of the product, the precautions against moisture that must be taken during shipping and storage, etc.
There are a wide variety of semiconductor packaging arrangements. Many state of the art package designs utilize a dielectric substrate formed from a suitable material such as BT (bizmaleimide trazine) to support the die and to provide appropriate routing to external contacts. Generally, the substrate has conductive elements (such as traces, and vias) that electrically connect landing pads on the top surface of the substrate to associated contacts on the back surface of the substrate (which in turn are used to electrically connect the die to external devices). The conductive elements are typically metallic (e.g. copper or gold) and any portions of the conductive elements that do not need to be exposed for wire bonding or soldering are often covered with a solder mask for protection.
One representative package arrangement using such a substrate is illustrated in FIG.
7
. Typically, a die
25
is mounted on the substrate
27
and wire bonded to landing pads on the top surface of the substrate. A plastic cap
30
is typically molded over the top surface of the substrate to protect the die
25
and bonding wires
32
. It is generally understood that the interfaces between adjacent layers in the resultant package (e.g., between the metalization and/or the solder mask and/or molding material and/or the substrate) can potentially delaminate which may lead to device failure. It is also generally understood that moisture penetration is one of the leading causes of delamination. Thus, there are continuing efforts to further improve substrate and package designs to reduce the probability of delamination and/or other environmentally induced failures in substrate based packages.
SUMMARY
In accordance with the present invention, a number of techniques and substrate arrangements have been proposed that working individually and in common have been found to significantly improve the environmental resistance of the resulting package. In one aspect, conductive pads (referred to herein as landing pads) on the top surface of a substrate are slightly undercut. This permits molding material applied during later packaging to flow into the undercut regions to help improve adhesion between the substrate and the molding material. The undercut landing pads can be formed in a number of ways. By way of example, in multi-layered landing pad structures an upper layer of each undercut landing pad may be designed to have a larger footprint than a corresponding lower layer of the undercut landing pad thereby forming the undercut. For example, one common layered landing pad structure contemplates the use of a copper or copper alloy base layer that is covered with a gold layer that is better suited for wire bonding (typically with a barrier layer interposed therebetween). In such a structure the gold and barrier layers can have a larger footprint than the copper layer thereby forming the undercut structure.
In another aspect, metallic die attach pads formed on the substrate are patterned to provide better adhesion between the substrate and a solder mask that covers the die attach pads. More specifically, the die attach pads are patterned to have a number of openings defined therein that leave corresponding portions of the substrate exposed. In substrates where a solder mask is applied over the die attach pad, the openings permit the solder mask to adhere directly to the substrate panel in the openings thereby strengthening the attachment of the solder mask to the substrate.
In still another aspect, elongated slots are provided in the solder mask such that the slots expose one or more rows of adjacent landing pads instead of simply the landing pads themselves. With this arrangement, some substrate material between adjacent landing pads is exposed which tends to improve the adhesion of molding material to the substrate.
REFERENCES:
patent: 5541450 (1996-07-01), Jones
patent: 6172419 (2001-01-01), Kinsman
patent: 6194782 (2001-02-01), Katchmar
patent: 6255740 (2001-07-01), Tsuji
patent: 6265759 (2001-07-01), Distefano
Lee Shaw Wei
Narvaez Glenn C.
Beyer Weaver & Thomas LLP
Huynh Andy
National Semiconductor Corporation
Nelms David
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