Substrate for semiconductor device and semiconductor device...

Details Substrate for semiconductor device and semiconductor device... Substrate for semiconductor device and semiconductor device...

2001-03-16

2003-09-30

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S678000

Reexamination Certificate

active

06627986

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a substrate for a semiconductor device and a method of fabricating a semiconductor device comprising the substrate and a semiconductor element or an integrated circuit (IC) chip mounted thereon. More particularly, the invention relates to a substrate comprising a dielectric base material (or, a dielectric core), inner terminals for electrical connection to the semiconductor element or chip, an inner circuit electrically connected to the inner terminals, and external terminals electrically connected to the inner circuit for electrical connection to an external circuit provided outside the substrate, and a method of fabricating a semiconductor device using the substrate.
2. Description of the Related Art
In recent years, there has been the increasing need to mount a semiconductor element or IC chip and its relating electronic components on a substrate at higher density. To meet this need, the Ball Grid Array (BGA) package and the Land Grid Array (LGA) package have been developed and used practically, thereby reducing the mounting area of the packaged semiconductor device including the element or chip.
The BGA package is a type of the surface-mounting packages of the semiconductor device, in which a semiconductor element or elements is/are mounted on a substrate and electrically connected to the inner circuit of the substrate. The element or elements and the substrate are encapsulated with a resin material in such a way that the bottom of the substrate is exposed from the encapsulation material, forming a surface-mounting package. Electrodes, which are electrically connected to the element or elements, are formed on the flat bottom of the package (i.e., the substrate) in the form of grid array. Metal or conductive balls (e.g., solder bumps) are attached to the respective electrodes as external terminals for electrical connection to an external circuit provided outside the package.
The LGA package is another type of the surface-mounting packages of the semiconductor device, in which a semiconductor element or elements is/are mounted on a substrate and electrically connected to the inner circuit of the substrate. The element or elements and the substrate are encapsulated with a resin material in such a way that the bottom of the substrate is exposed from the encapsulating material, forming a surface-mounting package. This configuration is the same as the BGA package. Unlike this, Electrode pads (i.e., lands), which are electrically connected to the element or elements, are formed on the flat bottom of the package (i.e., the substrate) in the form of grid array. The pads or lands serve as the external terminals and thus, no metal balls (i.e., bumps) are attached thereto.
FIGS. 1 and 2
show an example of the conventional substrate used for the semiconductor device with the surface-mounting packages of this type.
FIG. 1
shows the top view of a part of the substrate while
FIG. 2
shows the bottom view thereof.
The conventional substrate
110
shown in
FIGS. 1 and 2
comprises a rectangular plate-shaped, rigid, dielectric core
111
having an upper surface and a lower surface. The core
111
has a mounting area
111
a
on its upper surface and a land area
111
b
on its lower surface. A semiconductor element or IC chip (not shown) is mounted in the mounting area
111
a
in a later process. Lands
120
as external terminals are arranged in the form of array in the land area
111
b,
as shown in FIG.
2
. The core
111
is typically made of dielectric material, such as woven glass cloth impregnated with epoxy resin.
A patterned, conductive layer is formed on the upper surface of the core
111
, forming inner wiring lines
113
and inner terminals
114
. The conductive layer is typically made of a copper foil that has been etched to have a desired pattern. The wiring lines
113
extend approximately radially from the neighborhood of the periphery of the area
111
a
toward the outside. The terminals
114
, which are located in the mounting area
111
a,
are connected to the inner ends of the respective wiring lines
113
. The terminals
114
are used for electrically connection to a semiconductor element or an IC chip (nor shown) to be mounted on the substrate
110
by way of thin metal wires.
A conductive runner
117
is formed on the upper surface of the core
111
. The runner
117
is located near one of the edges of the core
111
and electrically connected to part of the inner wiring lines
113
. The runner
117
is used for facilitating the separation of the substrate
110
in a molding process of a semiconductor element or an IC chip mounted on the core
111
.
Another patterned, conductive layer is formed on the lower surface of the core
111
, forming inner wiring lines
119
and external terminals or lands
120
. The conductive layer is typically made of a copper foil that has been etched to have a desired pattern. The wiring lines
119
extend approximately radially from the inside of the land area
111
b
toward the outside. The terminals or lands
120
are connected to the inner ends of the respective wiring lines
119
and located in the area
111
b.
The lands
120
are used for electrically connection to an external circuit provided outside the substrate
110
.
Through holes
115
are formed to vertically penetrate the core
111
to interconnect the upper and lower surfaces of the core
111
with each other. The upper openings of the holes
115
are overlapped with the respective wiring lines
113
outside the mounting area
111
a
while the lower openings of the holes
115
are overlapped with the respective wiring lines
119
. Although not shown, the inner surfaces of the respective holes
115
are covered with a conductive layer such as a plated solder layer, in other words, the holes
115
are so-called “plated through holes”. Therefore, the wiring lines
113
on the upper surface of the core
111
are electrically connected to the respective wiring lines
119
on the lower surface thereof.
In the configuration shown
FIGS. 1 and 2
, the core
111
has a simple dielectric layer including no wiring layers therein. However, if the core
111
has a multilayer wiring structure including inner wiring layers and inner dielectric layers laminated together, the through holes
115
are used to electrically connect the specific wiring lines
113
and
119
to the inner wiring lines as well.
The upper surface of the core
111
is entirely covered with a dielectric, solder resist layer
118
except for the region
118
a
exposing the mounting area
111
a
and the region
118
b
exposing the runner
117
. The lower surface of the core
111
is entirely covered with a dielectric, solder resist layer
122
except for the region exposing the lands
120
. Therefore, the wiring lines
113
and
119
and the top and bottom openings of the through holes
115
are actually invisible from the outside. However, to clarify the configuration of the substrate
110
, they are illustrated to be visible in
FIGS. 1 and 2
.
Additionally, the core
111
is typically formed to be a strip, including a plurality of the structure shown in
FIGS. 1 and 2
. In this case, the structure of
FIGS. 1 and 2
are usually aligned at equal intervals in a single direction on the core
111
.
When a semiconductor device is fabricated using the substrate
110
, a specific semiconductor element or IC chip (not shown) is mounted on the upper surface of the substrate
110
(i.e., the core
111
) in the mounting area
111
a.
Next, the electrodes or bonding pads of the element or chip and the inner terminals
114
are mechanically and electrically connected to each other with thin metal wires (not shown). Thereafter, the element or chip, the metal wires, and the terminals
114
are encapsulated with a sealing or encapsulating resin material (not shown) on the upper surface of the substrate
110
. If the core
111
includes a plurality of the structure shown in
FIGS. 1 and 2
, these process steps are conducted for each of the mount

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