Substrate for evaluation

Details Substrate for evaluation Substrate for evaluation

2006-11-13

2009-06-30

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C438S692000, C438S687000, C438S626000

Reexamination Certificate

active

07554199

ABSTRACT:
The CMP technology is provided for a damascene wiring structure having a plural-layer wiring that is excellent in flatness and resolvability of Cu residue. An evaluation substrate is provided for evaluating the condition of a CMP that is employed for configuring a semiconductor device having a plurality of wirings in a vertical direction, and the evaluation substrate comprises: a substrate; a first groove formed on the substrate; a second groove formed on the substrate; and wiring material provided in the first groove and the second groove, wherein a depth of the second groove is shallower than that of the first groove.

REFERENCES:
patent: 6281114 (2001-08-01), Lin et al.
patent: 6514853 (2003-02-01), Matsubara
patent: 2006/0197228 (2006-09-01), Daubenspeck et al.
patent: 2001-007114 (2001-01-01), None

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