Substrate for a semiconductor package having improved I/O pin bo

Details Substrate for a semiconductor package having improved I/O pin bo Substrate for a semiconductor package having improved I/O pin bo

1986-03-24

1987-12-22

Ramsey, Kenneth J.

Electricity: electrical systems and devices

Miscellaneous

H01L 2348

Patent

active

047149825

ABSTRACT:
A substrate for an integrated circuit semiconductor package with I/O pins joined to the bottom surface, the improvement being the combination of solder wettable pin pads on the bottom surface of the substrate, I/O pins with a diameter less than the diameters of the pin pads, and a brazing material of an alloy that includes Ag, and a metal selected from the group consisting of In and Sn, and mixtures thereof, that exhibits a mushy zone over a predetermined temperature range, the metal disposed only between the pins and pin pads.

REFERENCES:
patent: 2568242 (1951-09-01), Matteson
patent: 2606362 (1952-08-01), Martin et al.
patent: 4182628 (1980-01-01), D'Silva
patent: 4418857 (1983-12-01), Ainslie et al.
patent: 4488673 (1984-12-01), Hopper
patent: 4518112 (1985-05-01), Miller et al.
patent: 4542438 (1985-09-01), Yamamoto
IBM Technical Disclosure Bulletin, vol. 25, No. 2, p. 571 (Jul. 1982), vol. 26, No. 1, p. 229 (Jun. 1983).

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