Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2007-06-12
2007-06-12
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185260, C365S185270, C365S185190, C365S185180, C365S185120, C365S185170
Reexamination Certificate
active
11198261
ABSTRACT:
A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.
REFERENCES:
patent: 4163985 (1979-08-01), Schuermeyer et al.
patent: 4616340 (1986-10-01), Hayashi et al.
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4821236 (1989-04-01), Hayashi et al.
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5136540 (1992-08-01), Hayashi et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5216269 (1993-06-01), Middelhoek et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5594685 (1997-01-01), Bergemont et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5703808 (1997-12-01), Makwana et al.
patent: 5739569 (1998-04-01), Chen
patent: 5742541 (1998-04-01), Tanigami et al.
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5808937 (1998-09-01), Chi et al.
patent: 5825064 (1998-10-01), Hayashi et al.
patent: 5867425 (1999-02-01), Wong
patent: 5872732 (1999-02-01), Wong
patent: 5886928 (1999-03-01), Makwana et al.
patent: 5896315 (1999-04-01), Wong
patent: 5978269 (1999-11-01), Bergemont et al.
patent: 5998826 (1999-12-01), Hung et al.
patent: 6026028 (2000-02-01), Lin et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6060742 (2000-05-01), Chi et al.
patent: 6088263 (2000-07-01), Liu et al.
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6091635 (2000-07-01), Chi et al.
patent: 6111788 (2000-08-01), Chen et al.
patent: 6133604 (2000-10-01), Chi
patent: 6188604 (2001-02-01), Liu et al.
patent: 6281075 (2001-08-01), Yuan et al.
patent: 6373746 (2002-04-01), Takeuchi et al.
patent: 6456528 (2002-09-01), Chen
patent: 6522580 (2003-02-01), Chen et al.
patent: 6656792 (2003-12-01), Choi et al.
patent: 6771536 (2004-08-01), Li et al.
patent: 6781877 (2004-08-01), Cernea et al.
patent: 6980471 (2005-12-01), Samachisa
patent: 2002/0181283 (2002-12-01), Ghodsi
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2003/0147278 (2003-08-01), Tanaka et al.
patent: 2004/0057283 (2004-03-01), Cernea
patent: 2004/0061168 (2004-04-01), Cappelletti et al.
patent: 2004/0130941 (2004-07-01), Kan et al.
patent: 0 393 737 (1990-10-01), None
patent: 0 399 261 (1990-11-01), None
patent: 0 399 261 (1990-11-01), None
patent: 63-172471 (1987-07-01), None
Edited by Brown and Brewer, “Nonvolatile Semiconductor Memory Technology,” IEEE Press, Section 1.2, 1998, pp. 9-25.
Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pp. 741-744.
Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, IEDM 1998, pp. 987-990.
Eitan et al., “Substrate Hot-Electron Injection EPROM,”IEEE Transactions on Electron Devices, vol. ED-31, No. 7, Jul. 1984, pp. 934-942.
Wijburg et al., “VIPMOS—A Novel Buried Injector Structure for EPROM Applications,”IEEE Transactions on Electron Devices, vol. 38, No. 1, Jan. 1991, pp. 111-120.
Hemink, Gertjan, “VIPMOS—A Buried Injector Structure for Nonvolatile Memory Applications,” CIP-Gegevens Koninklijke Bibliotheek, Den Haag (Gegevens Royal Library-The Hague), 1992, pp. 1-147.
Ning, T.H. et al., “Emission Probability of Hot Electrons From Silicon Into Silicon Dioxide,” Journal of Applied Physics, vol. 48, No. 1, Jan. 1977, pp. 286-293.
Zhao, S. P., “P-Well Bias Dependence of Electron Trapping in Gate Oxide of n-MOSFETs During Substrate Hot-Electron Injection,” Electronic Letters, vol. 28, No. 22, Oct. 22, 1992, pp. 2080-2082.
Lin, Frank Ruei-Ling et al., “A Novel Hot Carrier Mechanism:Band-to-Band TunnelingHole InducedBipolarHotElectron (BBHBHE),” IEDM 99-741, IEEE, 1999, pp. 31.1.1-31.1.4.
Hu, C.-Y. et al., “Substrate-Current-Induced Hot Electron (SCIHE) Injection: A New Convergence Scheme for Flash Memory,” IEDM 95-283, IEEE, 1995, pp. 11.6.1-11.6.4.
Chen, I.C. et al., “Band-to-Band Tunneling Induced Substrate Hot-Electron (BBISHE) Injectipn: A New Programming Mechanism for Nonvolatile Memory Devices,” IEDM 89-263, IEEE, 1989, pp. 10.4.1-10.4.4.
Hemink, G.J. et al., “High Efficiency Hot Electron Injection for EEPROM Applications Using a Buried Injector,” Extended Abstracts of the 21stConference on Solid State Devices and Materials, Tokyo, 1989, pp. 133-136.
Hemink, G.J. et al., “Modeling of VIPMOS Hot Electron Gate Currents,” Microelectronic Engineering 15 (Elsevier Science Publishers), 1991, pp. 65-68.
Wijburg, R.C.M. et al., “VIPMOS, a Buried Local Injector for EPROMs,” 19thEuropean Solid State Device Research Conference, Berlin, 1989, pp. 915-918.
Mouthaan, Ton, “A Vertically Integrated Dynamic Ram-Cell: Buried Bit Line Memory Cell With Floating Transfer Layer,” Solid-State Electronics, vol. 29 No. 12, 1986, pp. 1289-1294.
Lohstroh, J., “Punch-Through Currents in P+NP+and N+PN+Sandwich Structures—I, Introduction and Basic Calculations,” Solid-State Electronics, vol. 24, No. 9, 1981, pp. 805-814.
Lohstroh, J., “Punch-Through Currents in P+NP+and N+PN+Sandwich Structures—II, General Low-Injection Theory and Measurements,” Solid-State Electronics, vol. 24, No. 9, 1981, pp. 815-820.
Lohstroh, Jan et al., “WAM 1.5: Punch-Through Cell for Dense Bipolar ROMs,” International Solid-State Circuits Conference, Feb. 15, 1978, pp. 20-21.
EPO/International Searching Authority, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” mailed in related Application No. PCT/US2005/027963, Feb. 3, 2006, 10 pages.
Parsons Hsue & de Runtz LLP
SanDisk Corporation
Tran Andrew Q.
LandOfFree
Substrate electron injection techniques for programming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Substrate electron injection techniques for programming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate electron injection techniques for programming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3839783