Substrate electric potential sense circuit and substrate...

Details Substrate electric potential sense circuit and substrate... Substrate electric potential sense circuit and substrate...

2001-05-22

2004-02-10

Fahmy, Wael (Department: 2814)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06690226

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a substrate potential detection circuit for allowing a stable substrate potential level to be generated and maintained.
BACKGROUND OF THE INVENTION
Semiconductor devices have been equipped with substrate potential generators (such as back bias generators) that generate a voltage potential to be applied to the substrate or a well. By applying a potential bias to the substrate, various improvements to circuit operation have been made.
In a semiconductor memory device, such as a dynamic random access memory (DRAM), the substrate has typically had a potential bias applied. This has been done for various reasons. One reason is to improve latch-up characteristics by decreasing the possibility of forward biasing p-n junctions that are formed between sources or drains of transistors and the substrate. Also, a biased substrate has the affect of decreasing junction capacitance. Another affect is an increase in threshold voltages of transistors formed in the substrate. In a DRAM memory array, a biased substrate can improve cell-to-cell isolation by keeping undesired transistors (thick field devices) from being formed between memory cells. It can also decrease sub-threshold leakage in the memory cell transistor by increasing the cell transistor's threshold voltage.
For example, in a conventional DRAM memory cell the threshold voltage V
T
of a memory cell transistor is about 1.2 V and the substrate potential (back bias potential) is set to about −2 V.
In order to decrease the chip size of a semiconductor memory, such as a DRAM, device sizes are continuously made smaller. In the memory cell array, the memory cell transistor can have a gate length that is reduced. This can cause the memory cell transistor's threshold voltage V
T
to be reduced, which can contribute to charge leaking from a memory cell capacitor through the transistor by way of sub-threshold leakage.
Also, due to the memory cell transistor gate length becoming smaller, the depletion region formed by the p-n junctions of the source/drain regions to the substrate can be excessively large with respect to the gate length. In order to narrow these depletion regions, a higher concentration of dopant is implanted in the substrate. However, the narrower depletion region results in a higher electric field intensity. This higher electric field intensity can result in an increased charge leakage from the memory cell storage capacitor to the substrate by way of the p-n junction.
These charge leakage paths from the memory cell storage capacitor shorten the amount of time that charge can be held on the capacitor. This affects data integrity, in particular, the pause/refresh characteristics of the DRAM and decreases the reliability of the DRAM.
It is desired to keep the V
T
of the memory cell transistor at an adequate value while providing a minimum gate length. However, the substrate potential needs to be set at about −0.5 V to limit the intensity of the electric field at the p-n junction formed from the memory cell capacitor contact (source/drain region of memory cell transistor) and the substrate.
Current may flow to the substrate during various operating conditions of a DRAM. One example of an operating condition in which a relatively large amount of current can flow to the substrate is a data sensing operation. In a DRAM, due to the destructive nature of a read and the large number of memory cells selected during a read of a single bit, a large number of sense amplifiers are activated simultaneously. Each sense amplifier is biased in such a condition that a relatively large amount of current is injected into the substrate during the sensing operation. This can drastically affect the substrate potential.
In order to keep the substrate potential at about −0.5 V, an accurate substrate potential detector circuit is needed. Based on an output of the substrate potential detector circuit a substrate potential generator (substrate pump) can either be enabled or disabled based on whether the substrate potential is above or below −0.5 V.
One example of a conventional substrate voltage detector circuit has been disclosed in Japanese Patent Publication No. Hei 2-3153. Referring now to
FIG. 1
, a conventional substrate voltage detector circuit as disclosed in Japanese Patent Publication No. Hei 2-3153 is set forth in a circuit schematic diagram and given the general reference character
100
.
Conventional substrate voltage detector circuit
100
includes P-type metal-oxide-semiconductor field effect transistors (MOSFET) (
101
,
103
, and
104
) and N-type MOSFETs (
102
and
105
). P-type MOSFET
103
has a source connected to supply voltage V
CC
, a drain connected to detection node N
2
and a gate connected to ground voltage V
SS
. P-type MOSFET
101
has a source connected to a source of N-type MOSFET
102
and a drain and gate connected to the substrate potential V
BB
. N-type MOSFET
102
has a drain connected to detection node N
2
and a gate connected to supply voltage V
CC
.
P-type MOSFET
104
has a source connected to supply voltage V
CC
, a drain connected to substrate level detect signal node N
3
, and a gate connected to detection node N
2
. N-type MOSFET
105
has a source connected to ground voltage V
SS
, a drain connected to substrate level detect signal node N
3
, and a gate connected to detection node N
2
. P-type MOSFET
104
and N-type MOSFET
105
form an inverter
106
.
The operation of conventional substrate voltage detector circuit
100
will now be described.
P-type MOSFET
103
and N-type MOSFET
102
have gate voltages that keep both MOSFETs (
102
and
103
) in a conducting state. P-type MOSFET
103
and N-type MOSFET
102
form a voltage divider circuit with P-type MOSFET
103
having a resistance of R
2
and N-type MOSFET
102
having a resistance of R
1
. If P-type MOSFET
101
is relatively large compared to P-type MOSFET
103
and N-type MOSFET
102
, the detection node potential V
A
at detection node N
2
is given by the following equation: V
A
=(R
1
/(R
1
+R
2
))×V
CC
+(R
1
/(R
1
+R
2
))×(V
BB
+V
T
), where V
T
is the threshold voltage of P-type MOSFET
101
.
When the detection node potential V
A
falls below the trip point of inverter
106
, substrate level detect signal node N
3
becomes logic high. When the detection node potential V
A
rises above the trip point of inverter
106
, substrate level detect signal node N
3
becomes logic low.
Because the detection node potential V
A
is dependent on the substrate potential V
BB
, when substrate potential V
BB
falls below a predetermined potential, level detect signal node N
3
becomes logic high. When substrate potential V
BB
rises above a predetermined potential, level detect signal node N
3
becomes logic low. When at a logic low, level detect signal N
3
activates an oscillator (not shown). When at a logic high, level detect signal N
3
disables the oscillator. The oscillator is connected to a substrate pump (also not shown) and in this manner, the substrate potential V
BB
is regulated.
Another example of a conventional substrate voltage detector circuit has been disclosed in Japanese Laid-Open Patent Publication No. Hei 6-303765. Referring now to
FIG. 2
, a conventional substrate voltage detector circuit as disclosed in Japanese Laid-Open Patent Publication No. Hei 6-303765 is set forth in a circuit schematic diagram and given the general reference character
200
.
Conventional substrate voltage detector circuit
200
includes voltage dividers
211
and
212
, differential amplifier
218
, inverters (
219
and
220
) and latching circuit
221
.
Voltage divider
211
includes resistors (
213
and
214
). Resistor
213
is connected between a supply voltage V
CC
and a reference node N
201
. Resistor
214
is connected between a reference node N
201
and a ground voltage V
SS
.
Voltage divider
212
includes resistors (
215
,
216
and
2

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