Substrate design of a chip using a generic substrate design

Details Substrate design of a chip using a generic substrate design Substrate design of a chip using a generic substrate design

2001-09-07

2003-03-04

Paladini, Albert W. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000

Reexamination Certificate

active

06528735

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and system of packaging a multi-chip module having the same sized dies and fabricating such a module.
2. Description of the Related Art
As very large scale integrated (VLSI) circuits, known as dies or chips, become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed of state of the art VLSI devices. Packaging of such devices is by use of multi-chip modules (MCMs), which are normally mounted onto cards or boards. These MCMs accept dies that are bonded to pads on a top surface metallurgy (TSM) layer of the MCM. These TSM pads are interconnected to a bottom surface metallurgy (BSM) layer through vias to pins on a bottom surface by using wiring, wherein the vias pass through multiple intermediary redistribution layers and wiring layers. The TSM layer typically has pads made by controlled collapse chip connections (commonly known as C-4). The BSM layer is solder-ball-connect technology. The MCM multi-chip module technology represents a revolutionary advance in packaging and provides the high-performance wiring needed to exploit the gains achieved by today's VLSI devices. The MCM technology is taught in U.S. Pat. No. 5,914,533, which is hereby incorporated by reference.
Present day high performance VLSI chips have a large number of external input/output connection (called I/Os), such as pads, wire bands or solder balls, to name a few. This goes hand in hand with a corresponding increase in the number of input/output (I/O) counts of a chip which is made possible by “flip-chip” technology that especially uses C4-technology, to build low cost, high performance, high I/O density assemblies. In these assemblies, metal bumps, studs, or balls of metals (collectively referred to herein as “bump-type” interconnections) are usually applied in a two dimensional array pattern, either directly to the active surface of a semiconductor chip, or alternatively, to an intermediate substrate carrier of the semiconductor chip. The assembly is made by flipping the active, bumped surface over and then aligning the bumps of the chip with corresponding pads on a substrate to which the electrical connection is to be made. The substrate may be either a part of a semiconductor chip package (such as the MCM, ceramic chip carrier, etc.) or a board level assembly.
FIG. 1
(similarly shown in U.S. Pat. No. 5,914,533) shows an exemplary MCM module
3
. The module carries chips
1
and
2
are connected to the module by the C4-balls
4
and
5
. The C4-balls
4
connect the signal I/Os of the chips
1
and
2
to the module whereas the solid C4-balls
5
connect the voltage and ground terminals of the chips
1
and
2
to the module
3
. In the redistribution area of the module
3
, the signals of the chips
1
and
2
are fanned out. This is necessary because of the narrow pitch (close spacing of pads)of the chip footprints. The redistribution section has the redistribution planes R
1
, R
2
, R
3
, R
4
, R
5
. . . R
14
as required. Each redistribution plane is interposed between power and ground GND mesh planes
6
. The redistribution planes contain horizontal signal wiring
9
to fan out the signals. The vertical connections in the module
3
are established by vertical vias
7
and
8
. The vertical vias
7
carry the signals and the vertical vias
8
carry power and ground. At the end of the redistribution section, logic service terminals (LST) provide the interface to the X/Y wiring area for larger size MCM when a large size chip is used. This X/Y wiring area is not always needed in smaller MCM designs and is optional. In such a case, the pins are then attached to the BSM layer. The X/Y wiring area comprises X/Y wiring planes which establish the connections from one chip to another chip or from one chip to the pins of the module
3
. Note that only two wiring plane pairs X
3
/Y
3
and X
4
/Y
4
are shown. The fan-out capability with low noise functioning in the redistribution section is limited to I/O counts of around 500 to 700 signals.
Present MCM packages are produced by MCM computer aided design (CAD) software tools that are available from Mentor Graphics Inc., Cadence Viewlogic Systems Inc. and LSI Logic Inc. Such tools can lay out the design of die on a substrate and package an MCM design, wherein each with a given number of I/Os is wired separately. For example, given a 10 mm chip, the design might require that the MCM design include a first substrate design having 300 I/Os, a second substrate design that has 400 I/Os, and a third substrate design that has 500 I/Os. Each redistribution section of these three substrate designs form a composite MCM substrate design which are separately designed and not replicated. This represents significant design effort.
The prior art has approached MCM packaging design problems by various techniques. U.S. Pat. No. 5,777,383 (hereinafter '383 patent) discloses a way to package a semiconductor chip, which incorporates a plurality of levels of interconnecting conductive layers within the package which selectively direct signals to and from pins of the die and/or the pins of the package. The '383 patent uses a single general purpose chip that can be fabricated in large quantities with the interconnect of the package is used to define the specific purpose, functionality and pinout of the final device.
U.S. Pat. No. 6,048,753 (hereinafter '753 patent) discloses a standardized bonding location process for making a semiconductor chip device, wherein the resulting device has standardized die-to-substrate bonding locations. The '753 patent die provides a standardized ball grid or other array of a particular size, pitch and pattern such that as the size, configuration or bond pad arrangement of the die changes, a standard substrate, (the term including lead frames) having a similarly standardized array of terminals or trace ends is used to form the semiconductor device. The '753 patent can use dies having markedly different circuitry, but a common array pattern with the same substrate or other carrier.
These CAD tools for packaging MCM generally require several unique substrate designs for a given physical (menu) chip size having varying number of I/Os for each die, resulting in much custom design effort to package the MCM. The above prior techniques taught in the patents '383 and '753 typically have redesigned the top surface metallurgy (TSM) layer to interface with each die forming part of the MCM by customizing the TSM layer that requires much denser wiring, which in turn generally requires more time, material and expense to produce a resulting MCM design.
The present invention, however, solves these and other problems resulting in a packaged substrate by an improved method as more fully described in the following description taken along with the accompanying drawings.
SUMMARY OF THE INVENTION
The invention provides a method for packaging substrates of multi-chip modules (MCM) by reusing a generic repeatable substrate design for chips or dies having the same physical size by using a menu die having the greatest number of I/O wiring interconnections between the TSM and bottom surface metallurgical (BSM) layers. This global substrate design is referred to as “generic” substrate design, and is modified to accommodate different substrate designs for other dies having the same physical size. With the invention a customized lower redistribution layer accommodates each of the different designs. Moreover, unused I/O signal leads are terminated in the redistribution layer above the BSM layer. The “generic” substrate design provides a repeatable upper redistribution section wherein the vias for the I/O wiring is the same which can be reused in all substrate designs.
When designing a different substrate design for a die that has the same physical size as the generic chip, but which has a fewer number of I/O wiring requirements, the “generic” substrate design is reused,

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