Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
1999-08-18
2001-05-15
Berhane, Adolf Deneke (Department: 2838)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
Reexamination Certificate
active
06232551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a substrate board structure. More particularly, the present invention relates to the substrate board of a lead-on-chip (LOC) package.
2. Description of Related Art
As semiconductor manufacturing passes into the deep submicron scale, dimensions of each semiconductor device shrink. Hence, each integrated circuit has a higher operating speed. Due to the large-scale miniaturization of devices, volume of a semiconductor package can be reduced. To reduce the size of a semiconductor package, the semiconductor industry has developed several types of package structures such as the lead-on-chip (LOC) or the chip-on-lead (COL). The silicon chip of these package structures is stacked directly on top of the conductive wires of a lead frame or a substrate board. Hence, there is no need to set aside a specific area for mounting the silicon chip, thereby reducing the volume of the package. Other methods of decreasing package volume include the use of a laminated substrate carrier for supporting the silicon chip and the formation of an area array for solder balls.
FIG. 1
is a schematic top view showing a conventional LOC substrate board. The substrate board
10
consists of copper layers and an insulation layer
12
stacked together and having a slot
11
in the middle. After a hole-drilling operation and a copper layer patterning operation, circuit lines
14
are formed on the substrate board surface for subsequent electrical connection with a chip. Each circuit line
14
is also connected to a bonding pad
16
and a ball pad
18
. Each bonding pad
16
is an area where the end of a conductive wire is bonded using a wire-bonding machine and each ball pad
18
is an area where a solder ball is attached. A solder mask
20
is formed over the substrate board
10
such that the bonding pads
16
and the ball pads
18
are exposed. In general, copper is used to form the circuit lines
14
. However, the surface of a copper layer can be easily oxidized to form a poor conductive layer. Therefore, to increase bondability of each bonding pads
16
with a conductive wire during a wire-bonding operation and each solder ball with a ball pad
18
, a layer of gold is usually plated on top.
To facilitate the electroplating of a gold film over the bonding pads
16
and the ball pads
18
, additional electroplating bars
22
are formed on the substrate board
10
connecting to all circuit lines
14
. After the electroplating bars
22
are appropriately connected to an electrode, electroplating gold can be carried out. However, before carrying out an open/short test (O/S test), electrical connections between the circuit lines
14
must be severed. To maintain substrate board integrity so that subsequent testing and packaging can be conveniently carried out, junctions between the circuit lines
14
and the electroplating bars
22
have to be cut by performing multiple half drillings. The process is laborious and time-consuming. In addition, the electroplating bars are positioned along the peripheral section of a substrate board. Hence, the required board area is increased, leading to a waste of board material.
FIG. 2
is a schematic top view of another conventional substrate board. As shown in
FIG. 2
, the electroplating bar
22
is different from the one in FIG.
1
. The electroplating bar
22
is located in the middle of the slot region
11
. The slot
11
is only made after the electroplating operation. In the slot-making process, electrical connections between the electroplating bar
22
and the circuit lines
14
are cut.
FIG. 3
is a magnified view of the area surrounding the slot
11
in FIG.
2
. As shown in
FIG. 3
, when the electroplating bar
22
is formed in the middle of the slot region, burrs
24
are likely to form on the edges of the cut surfaces. Hence, some of the circuit lines
14
may be short-circuited leading to poor product quality.
SUMMARY OF THE INVENTION
The present invention provides a substrate board structure capable of preventing burrs from forming around the slot of the board and hence improving the board quality.
The invention provides a substrate board having an electroplating bar inside a slot region of the board such that electrical connections between circuit lines and the electroplating bar can be severed when the board is cut to form a slot.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a substrate board structure. The substrate board is formed by stacking a plurality of circuit layers and insulation layers on top of each other. Each circuit layer has a plurality of circuit lines and every pair of neighboring circuit layers is isolated from each other by an insulation layer. The insulation layers further include a plurality of vias for connecting electrically with circuit line layers. The interior surface of each via is electroplated with a metal film and the remaining interior space of the vias is filled with a filler material. The substrate board further includes a central slot. The circuit layer on the substrate board surface has a plurality of first contact points and second contact points that are connected to various circuit lines. The first contact points are close to the slot. Circuit lines that connect to the first contact points extend forward to reach the vias along the edge of the slot. Since the vias are formed on the boundary of the slot region, a portion of the metallic film within the vias is exposed.
To form the substrate board structure of this invention, a substrate board comprising of a plurality of insulation layers and circuit layers stacked on top of each other is provided. Neighboring circuit layers are separated by an insulation layer. The substrate board has a slot region. Holes are drilled to form a plurality of vias on the substrate board. A few of the vias are formed in the boundary of the slot region. The interior surface of the vias is electroplated to form a metal film. The remaining space inside the vias is filled with a filler material. The circuit layer on a substrate board surface is patterned to form a plurality of circuit lines. Each circuit line on the board surface is also connected to a first contact point, a second contact point and an electroplating bar. The first contact points are closer to the slot region. The electroplating bar is inside the slot region. The circuit line that connects to a first contact point extends to a via on the boundary of the slot region and continues on to reach the electroplating bar. The electroplating bar is connected to an electrode and then the circuit lines are electroplated so that the surfaces of the first contact points and the second contact points are electroplated. Finally, a slot is formed by cutting out a piece in the slot region so that a portion of the metal film on the via sidewall is exposed.
Since the metallic film on the via sidewall is sandwiched between the filler material and the insulation layer alone a radius, burrs are less likely to form when the board is cut. Moreover, the severance of electrical connection between the circuit lines and the electroplating bar as well as the cutting of substrate boards to form a slot can be achieved in the same step.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 4865875 (1989-09-01), Kellerman
patent: 5025114 (1991-06-01), Braden
patent: 5480048 (1996-01-01), Kitamura et al.
patent: 5635671 (1997-06-01), Freyman et al.
patent: 5962810 (1999-10-01), Glenn
Berhane Adolf Deneke
Huang Jiawei
J.C. Patents
Subtron Technology Co. Ltd.
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