Substrate bias voltage generating circuit

Details Substrate bias voltage generating circuit Substrate bias voltage generating circuit

2001-06-14

2004-03-02

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S536000, C331S046000

Reexamination Certificate

active

06700434

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a substrate bias voltage generating circuit which is applicable to a semiconductor memory.
BACKGROUND OF THE INVENTION
In general, a back bias voltage (VBB voltage, hereinafter) of a semiconductor the memory is generated as a voltage lower than a low voltage power source which is required for activating the semiconductor memory, and the VBB voltage is used for the following reasons:
Firstly, if a VBB voltage is applied, i.e., if the substrate-side memory is lowered in voltage, it is possible to prevent a positive
egative junction in a memory chip from being partially biased by a forward voltage, and to prevent data in a memory cell from being destroyed and to prevent the latch-up phenomenon.
Secondly, a variation in threshold voltage of a MOS transistor caused by bulk effects can be reduced to stabilize an operating state of the circuit. That is, if the VBB voltage is applied, it is possible to reduce the magnitude of variation in the threshold voltage caused by a variation in source potential. This means that a rising width of a word line can be reduced, and reliability of the device can be enhanced.
Thirdly, if the VBB voltage is applied, it is possible to increase a threshold voltage of a parasitic MOS transistor. If the threshold voltage of the parasitic MOS transistor is increased, junction breakdown voltage is improved and the current is reduced.
Fourthly, if the VBB voltage is applied, it is possible to reduce the capacitance of a positive
egative junction formed between an N
+
source drain region and a P well region of an NMOS transistor. With this effect, the circuit operation speed is increased, a parasitic capacitance on a bit line is reduced, and the capacity of cell data transmitted to the bit line is increased.
As described above, the substrate bias voltage generating circuit for generating a VBB voltage is indispensable for stably operating a semiconductor device.
FIG. 23
is a block diagram showing a schematic structure of a conventional substrate bias voltage generating circuit. As shown in
FIG. 23
, a general conventional substrate bias voltage generating circuit comprises an active ring oscillator
111
and an active pump circuit
112
which are activated in an active mode during which data is read out from and written to a memory, a standby ring oscillator
121
and a standby pump circuit
122
which are activated in a standby mode during which data is not read out from or written to the memory.
Next, the operation of the conventional substrate bias voltage generating circuit will be explained.
FIG. 24
is a flowchart showing the operation of the conventional substrate bias voltage generating circuit. First, in the substrate bias voltage generating circuit, a detection circuit (not shown) detects whether an operation state of a memory such as DRAM is the active mode or standby mode (step S
1001
).
When the operation state is the active mode, the detection circuit outputs an act signal to the active ring oscillator
111
and the active pump circuit
112
, and they are brought into active state (steps S
1002
, S
1003
). With this operation, a large negative VBB potential is generated, which is suitable for high speed operation (step S
1006
), and the VBB potential is supplied to a substrate of a memory.
On the other hand, when the operation state is the standby mode, the detection circuit outputs a standby signal to the standby ring oscillator
121
and the standby pump circuit
122
and they are brought into the standby state (steps S
1004
, S
1005
). With this operation, a small negative VBB potential is generated, which reduces power consumption (step S
1006
), and the VBB potential is supplied to the substrate of the memory.
Initially, the conventional substrate bias voltage generating circuit comprised only one ring oscillator and one pump circuit. However, in order to reduce the electric current consumption and to supply VBB voltage having larger absolute value to the pump circuit, in the above-described structure each of the ring oscillators and pump circuits is divided into active-type and standby-type.
If the capacity of the memory is increased, however, the supply ability of VBB voltage must also be increased and thus, the area of the substrate bias voltage generating circuit must be increased. Therefore, it is desired to reduce the area of the substrate bias voltage generating circuit.
A yield of a memory has been enhanced recently and thus, it is necessary to also enhance a yield of the substrate bias voltage generating circuit by saving circuits which were assumed as being defective circuit heretofore.
With tendencies of thinning and lightening the semiconductor electronic device, it is required to reduce the power consumption. Therefore, it is necessary to reduce the electric current consumption of the substrate bias voltage generating circuit also.
In recent years, electrical equipment is controlled by exchanging data between three elements, i.e., a memory, a microcomputer, and a logic circuit. As processing technology has progressed, it has become possible to incorporate an LSI into electrical equipment, and a so-called memory incorporated ASIC (Application Specific Integrated Circuit) in which the above three elements are formed into one chip has received attention.
This memory-incorporated ASIC is different from a general combination of the memory and the microcomputer in that not only the size can be made compact, but also a bus width is widened so that the data transmission speed can be increased and power consumption can be reduced. That is, in this memory-incorporated ASIC, since it is necessary to design memories of various capacities depending upon requirements, there is a problem that it is not always the best to utilize a substrate bias voltage generating circuit for a conventional standardized memory capacity.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a substrate bias voltage generating circuit in which a tuning mechanism of a VBB voltage is provided in a ring oscillator and a pump circuit so that an area occupied by the circuit is reduced, power consumption is reduced, it is easy to design the circuit and the yield is enhanced.
According to the substrate bias voltage generating circuit of one aspect of the present invention, different oscillation outputs output by respective detector circuits for each detection signal are obtained from ring oscillators corresponding to every detector circuit. Further, a selector is made to selectively output one of the oscillation outputs. Therefore, one pump circuit can be commonly used.
According to the substrate bias voltage generating circuit of another aspect of the present invention, different oscillation outputs corresponding to the plurality of detector circuits are generated by one ring oscillator and at least one frequency divider. Accordingly, a plurality of ring oscillators become unnecessary.
According to the substrate bias voltage generating circuit of still another aspect of the present invention, in the one pump circuit, the power source voltage to be supplied to all or a portion of the semiconductor device constituting the substrate bias voltage generating circuit is switched in accordance with the plurality of different detection signals. Therefore, the supplying ability of the substrate bias voltage can be changed.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


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patent: 5877651 (1999-03-01), Furutani
patent: 5999009 (1999-12-01), Mitsui
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patent: 6278316 (2001-08-01), Tanzawa et al.
patent: 6337595 (2002-01-01), Hsu et al.
patent: 6400216 (2002-06-01), Kim et al.
patent: 59-162690 (1984-09-01), None
patent: 1-243288 (1989-09-01), None
patent: 2-290051 (1990-11-01), None

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